Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time and resource-consuming. Therefore, it is not supported on chips that are not produced in high volume due to the low return on investment. EeLADA was explored as an alternative. Although its feasibility has been proven in a previous report, the localization capability or diagnostic resolution is limited to at best failing bit-lines. This work enhances this technique to achieve a resolution down to bit-cell level with an accuracy of less than 5 µm.

Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic emission micrographs that are caused by open defects in digital logic. This paper presents a methodology incorporating layout-aware trace analysis and post schematic extraction with test bench analysis to enhance the diagnostic resolution on the suspected defective net(s).

Most modern system on-chip incorporates a significant amount of embedded memories to achieve a reduced power consumption, higher speed and lower cost. In general, such memories are evaluated using built-in self-testing methods and in the event of a failure, bitmapping is heavily relied on for fault localization to guide subsequent failure analysis. However, a fast yield ramp can be impeded when bitmapping is not enabled in time or is inaccurate. This work studies the feasibility of employing electrically-enhanced LADA as an alternative method to debug embedded memory failures. Results are presented to demonstrate that the resolution of localization depends on the precision of diagnostic test pattern used and the laser spot size.

In a failure event, circuit schematic analysis usually follows after fault isolation to increase the success rate. However, analyzing an extracted netlist of the isolated sub-circuit can be messy. Manual circuit translation from layout where the analyst is in control of the cell instance placement is one way to overcome this challenge. Although it is neater and intuitive for analysis, it can be time consuming to create the schematic. To analyze circuits in a systematic manner, cross-mapping between layout and schematic contents is the most commonly recognized approach. However, at times, cross-mapping alone is insufficient and some further simplification procedures are favorable. This paper describes the challenges and illustrates using real case studies, how schematics re-ordering and substitutions can be useful to simplify and enhance circuit analysis. These procedures can be implemented in an automated manner to enhance turnaround time for analysis.

This paper illustrated the beauty of AFP nanoprobing as the critical failure analysis tool in resolving the one-time programmable (OTP) non-volatile memory data retention failures through electrical simulation in wafer fabrication. Layout analysis, electrical simulation using Meilke’s method, UV erase methodology (to differentiate between mobile ion Meilke’s method contamination and charge trap centers) and a few other FA approaches were employed to determine the different root causes in the three OTP failure case detailed in this paper.. These include SiN trap center issue, poly stringers and abnormal layer at the initial CESL (Contact etch stop layer) nitride. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.

This paper places a strong emphasis on the importance of applying the correct FA approach in physical sample preparation to identify hidden defects that can be easily removed during analysis. A combination of mechanical parallel polishing and chemical etching was used during the sample preparation after electrical fault isolation. Such a combination is both effective and efficient in identifying the single Via punch-through from a sea of Via in MIM structure as well as finding the thin layer of barrier bridging under the Al metal. It serves as a quick way to verify any suspect without time consuming FIB progressive cuts at the hotspot location which sometimes turns out to be an induced spot with a defect located at other site due to the circuitry connection. It would serve as a good reference to wafer fab that encountered such issues.

This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.

This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.

This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 μs to 2 μs. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.

In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.

With the rapid development of semiconductor manufacturing technologies, IC devices evolve to smaller feature sizes and higher densities, and thus the task of performing successful failure analysis (FA) is becoming increasingly difficult. Device miniaturization often requires high spatial resolution fault isolation and physical analysis [1]. To cater to the shrinking of devices, extensive process improvements have been conducted at the front-end-of-line (FEOL) structures. As a result, among the numerous types of defects leading to chip failure, FEOL defects are becoming more common for devices of advanced tech nodes [2]. Therefore, it becomes more complexity and difficulty on searching the physical defect. Sample preparation is a key activity in material and failure analysis. In order to image small structures or defects it is often necessary to remove excess material or layers hiding the feature of interest. Removing selected layers to isolate a structure is called delayering. It can be accomplished by chemical etching using liquid or plasma chemistry, or by mechanical means, by polishing off each unwanted layer.

Dynamic Laser Stimulation (DLS) technique have met with great success over the past few years in helping failure analysis engineer to tackle different type of soft failures. DLS is widely applied to devices presenting an abnormal behavior for any electrical parameter, such as operating voltage and frequency. This paper showcase another successful implementation of DLS technique, combined with design analysis to reveal the root cause for SRAM soft failure.

In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.

A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.