Deprocessing and probing are two quintessential steps in the physical failure analysis (PFA) and competitive analysis of integrated circuits (ICs). Typically, these steps are accomplished using multiple tools, which include polishers, electron microscopes, and probers. To combat the aggressive back-end-of-line (BEOL) scaling which has significantly decreased the controllability of manual polishing, gas-assisted Xe plasma FIB has been employed to achieve large area uniform delayering. Combined with an in-situ probing capability within the plasma FIB, the iterative process of juggling between tools is streamlined into a seamless process. In this paper, the successful integration of Prober Shuttle and plasma FIB to isolate and visualize real defects on sub-20 nm microprocessor chips are presented.

Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.

Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry.

This paper uses an interesting case study to highlight high-resolution pulsed thermal-induced voltage alteration (TIVA) with solid immersion lens (SIL) as a technique to isolate a temperature-sensitive failure in mixed-signal circuitry, followed by circuit analysis and nanoprobing to confirm a drive strength issue caused by a process change.

Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

The spatial resolution and sensitivity of laser induced techniques are significantly enhanced by combining refractive solid immersion lens technology and laser pulsing with lock-in detection algorithm. Laser pulsing and lock-in detection enhances the detection sensitivity and removes the ‘tail’ artifacts due to amplifier ac-coupling response. Three case studies on microprocessor devices with different failure modes are presented to show that the enhancements made a difference between successful and unsuccessful defect localization.

Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.

For time resolved hot carrier emission from the backside, an alternate approach is demonstrated termed single point PICA. The single point approach records time resolved emission from an individual transistor using time-correlated-single-photon counting and an avalanche photo-diode. The avalanche photo-diode has a much higher quantum efficiency than micro-channel plate photo-multiplier tube based imaging cameras typically used in earlier approaches. The basic system is described and demonstrated from the backside on a ring oscillator circuit.

Thermal beam induced techniques such as Thermally Induced Voltage Alteration (TIVA), Seebeck Effect Imaging (SEI) [1] and Optical Beam Induced Resistance Change (OBIRCH) [2] have been used for localization of reliability related faults in integrated circuits over the last few years. In this paper, we describe several approaches to optimize the detection of thermal beam induced phenomenon. In the first method, we have improved control of the laser scanning system to define a specific dwell time at each pixel. Secondly, we utilized a voltage source in series with an inductor to detect the induced voltage changes as the laser is scanned across the device. Finally, we employed a pulsed laser and a lock-in signal processing technique to increase the signal-tonoise ratio.

The Single Contact Optical Beam Induced Currents (SCOBIC) is a new failure analysis technique, which allows the imaging of junctions by a single connection to the substrate or power pin of an integrated circuit. Modern packaging technologies and multi-layer metallizations has increased the need for backside IC failure analysis. In this paper, the SCOBIC technique is used to image junctions from the die backside. The implementation of backside SCOBIC system is discussed. Application of the SCOBIC technique from both the frontside and backside of CMOS and NMOS devices are presented.