Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.