This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.

Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing, in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.

With the advancement in technology and lower operating voltage, new standards have evolved in circuit layout and design. Some of these new standards have increased the difficulties of the physical failure analysis process, especially on the front-end. The phenomenon described in this paper is the unusual voltage contrast (VC) and conductive atomic force microscope (C-AFM) curve on a non-isolated active region. The model and mechanism are demonstrated for front-end failure analysis. Based on this, the solution for analysis is investigated.

This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.