The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Damage on the top metal layer caused by backend packaging processes often results in unlocalizable electrical failures like column select fails in DRAM products. Consequently, crosssections through an exact address are unhelpful. Decapping from the front side of the die by removing the package (Top- Down preparation), only uncovers the damaged die area. The root cause is removed with the package. A preparation method that preserves the package at the failure (Bottom-Up preparation) is necessary. This paper presents a preparation method for investigations and assessment of backend related problems by removal of the Si-die from the back side, leaving the package and connections layers free for a quick and reliable review. Typical applications described here are the localization of imprint-originated fails or monitoring of the bonding processes.

A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical defect, they give a starting point for further electrical analysis leading to the root cause of the failure. The paper will present a case study on a state-of-the art DRAM device failing with a timing problem. Especially the test aspects as well as the setup for the temperature dependent localization will be described. Finally an interpretation of the results will be proposed.

The electrical interface, in terms of a reliable, low ohmic and defined connection with the device or die is the most relevant aspect in the characterization of products. Bad or undefined contacts inhibit an exact assessment of the functionality. This paper describes different contact related failures analyzed in our lab and gives the solutions we used to solve the problems. Especially an electroless (nickel)-gold plating method has been optimized and is described in details. Low ohmic and reliable contacts can be produced; the paper shows several applications to improve the contact quality in different domains of the failure analysis business

Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test patterns due to the multiple possibilities for leakage of the cell itself [1]. A direct characterization of the access transistor is not possible because of the missing contact on the drain side (Deep Trench side). A tentative method to overcome this problem has been reported by G. Zimmermann, by using a front side Focused Ion Beam (FIB) contact to access the drain [2]. Unfortunately this method is limited to “coarse” technologies down to 0.15µm due to the resolution of the FIB probe. In addition, the backside contacting via trench allows the measurement of resistance and/or leakage elements at the interface buried strap, Poly 1-Poly 2 within DT (process conditioned). This paper presents an innovative way to contact the access transistor from the backside of the die, using the deep trench of the cell itself as connection to the drain of the investigated device. The backside contact to the polysilicon filled DT is the key aspect of the method and is realised by backside Focused Ion Beam.