In this paper, we demonstrate three approaches to enhance the topographical contrast of infrared images obtained from lockin thermography (LIT). Infrared imaging, particularly LIT, is one of the extensively used techniques for failure analysis (FA) in the semiconductor industry. However, low-contrast topography images are obtained at room temperature from conventional LIT due to poor emissivity contrast in the devices and the limitation on the performance of the infrared camera. The gray-scale topographical contrast is improved by 85% when the device under test is heated from room temperature to 75°C, using a printed circuit board heater. Furthermore, a heat-assisted LIT approach is proposed and demonstrated at the die level on an electrically leaky silicon interposer sample. The topographical contrast and the signal intensity of the hotspot obtained are enhanced when compared to the classical LIT, which is performed at room temperature. Further, the dual LIT approach is developed to reduce the thermal budget of the heat-assisted approach. The hotspot amplitude and improved topography image are obtained from two consecutive lock-in measurements. In addition, the topography image from this technique is obtained by averaging several hundred frames from the camera for a period of ten minutes, which results in an image that is less susceptible to input noise levels. To increase the throughput of the FA process, quadrature lock-in thermography, a dual-purpose measurement technique is shown. A high-contrast topography image and the hotspot location are obtained from the same lock-in thermogram by performing trigonometric conditioning. The throughput from this approach is the same as the classical LIT technique.

Lock-In Thermography is an established nondestructive method for analyzing failures in microelectronic devices. In recent years, a major improvement made it possible to acquire time-resolved temperature responses of weak thermal spots, greatly enhancing defect localization in 3D stacked architectures. One limitation, however, is in the method used to determine defect depth, which is based on the numerical estimation of the delay between excitation and thermal response inferred from the value of the lock-in phase. In structures where the region between the origin of the defect and sample surface is partially or fully transparent to infrared signals, interference between radiated and conducted signal components largely falsifies the phase value on which the classical depth estimation relies. In the present study, blind source separation based on independent component analysis was successfully used to separate interfering signal components arising from direct thermal radiation and conduction, resulting in a precise estimation of the defect depth.

This presentation provides an overview of the tools and techniques that can be used to analyze failures in semiconductor devices made with 3D technology. It assesses the current state of 3D technology and identifies common problems, reliability issues, and likely modes of failure. It compares and contrasts all relevant measurement techniques, including X-ray computed tomography, scanning acoustic microscopy (SAM), laser ultrasonics, ultrasonic beam induced resistance change (SOBIRCH), magnetic current imaging, magnetic field imaging, and magneto-optical frequency mapping (MOFM) as well as time domain reflectometry (TDR), electro-optical terahertz pulsed reflectometry (EOTPR), lock-in thermography (LIT), confocal scanning IR laser microscopy, infrared polariscopy, and photon emission microscopy (PEM). It also covers light-induced voltage alteration (LIVA), light-induced capacitance alteration (LICA), lock-in thermal laser stimulation (LI-TLS), and beam-based techniques, including voltage contrast (VC), electron-beam absorbed current (EBAC), FIB/SEM 3D imaging, and scanning TEM imaging (STEM). It covers the basic principles as well as advantages and limitations of each method.

This paper discusses the implementation of GHz-Scanning Acoustic Microscopy (GHz-SAM) into a wafer level scanning tool and its application for the detection of delamination at the interface of hybrid bonded wafers. It is demonstrated that the in-plane resolution of the GHz-SAM technique can be enhanced by thinning the sample. In the current study this thinning step has been performed by the ion beam of a ToF-SIMS tool containing an in-situ AFM, which allows not only chemical analysis of the interface but also a well-controlled local thinning (size, depth and roughness).

This paper demonstrates the application of GHz-SAM for the detection of local non-bonded regions between micron-sized Cu-pads in a wafer-to-wafer hybrid bonded sample. GHz-SAM is currently the only available non-destructive failure analysis technique that can offer this information on wafer level scale, with such high resolution.

Tremendous research efforts have been devoted particularly to the development and improvement of through silicon vias (TSV) in order to provide a key enabling technology for vertical system integration. To achieve high processing yield and reliability efficient failure analysis techniques for process control and root cause analysis are required. The current paper presents an advanced approach for non-destructive localization of TSV sidewall defects applying high resolution Lock-in Thermography and Photoemission Microscopy imaging and defocusing series.

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.

This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

In this paper we described a technique which is not commonly used for failure analysis: Orientation Imaging Microscopy (OIM). We demonstrated that it offers unique opportunity for failure analysis of Cu bonding and interconnects. Additionally to its main application: texture analysis, it can also reveal early stages of oxidation of Cu bond pads and interconnects. A link has been made between oxidation and bondability. OIM can also show areas of the wire bond where the deformation concentrates due to the bonding process.

In this paper we discuss reliability and failure analysis issues of RF-MEMS capacitive switches. We describe specific instrumentation and methods that can be used for testing and examination of these switches. These include SEM, AFM, SAM, static and dynamic optical investigation and electrical lifetime testing. Processing as well as testing and packaging issues are discussed.

To investigate the mechanical behavior and failure modes of micro-electromechanical systems (MEMS), a high resolution optical tool capable of imaging both fast and slow movements in three dimensions on a microscopic scale is almost mandatory. We report the first experiments with a new tool, which provides the necessary speed and resolution. First, some common failure modes in MEMS are discussed, as are the possibilities of optical inspection methods to deal with them. We show that the system we describe may be used to monitor the resonances and small but fast movements of a MEMS device, to image erratic behavior, stuck parts, and so on. Furthermore, slow deformations, for example of expansion due to temperature changes, can be monitored with high resolution, and give information on deformation or delamination of layers.

In this paper, Photon Emission Microscopy (PEM) and micro-Raman Spectroscopy (μRS) are applied for temperature profile measurements and failure characterization in gg-nMOS ESD protection devices. The measurements were carried out in avalanche and snapback biasing conditions. A correlation between the temperature profile obtained by μRS and the light emission location, measured by PEM, is observed for non-degraded devices. In addition, ESD-degraded devices were studied. PEM, μRS, Spectroscopic Photon Emission Microscopy (SPEM) and electrical measurements were used to investigate the origin of the light emitted at the failure site. They showed that the light emission occurring at the failure site is due to impact ionization.