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1-7 of 7
Ian Kearney
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 65-73, October 30–November 3, 2022,
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High-power, diode pump laser modules with improved 0.25% antireflective (AR) coating exhibited low (weak) or zero (dead) power emitters after 1000+ hours life-test. Catastrophic optical mirror damage (COMD) was suspected due to a facet coating upgrade but was not physically observed. Electroluminescence ‘fingerprinting’ lent to a contradictory catastrophic bulk damage (COBD) failure mechanism. The Customer wished to clearly understand how an AR coating change caused COBD and not COMD. This paper emphasizes how the astute failure analyst must remain a ‘conscious observer’ deploying concerted analysis steps to truly unmask root-cause amidst conflicted stakeholders.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 398-402, November 5–9, 2017,
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The degraded performance of a power MOSFET affects customer system reliability and consumer perceptions of quality. Building a reliable product and associated application specific lifetime models to predict the suitability of a power device for a given solution can enable competitive advantages, increased quality, enhanced performance and result in market share gains. This paper describes the methodology employed to configure an application specific reliability test, the failure rates and modes observed, the package modelling, and design improvements implemented. The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements in areas most relevant to customer concerns while at the same time adding credibility to specified product limits.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 419-423, November 5–9, 2017,
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Photoluminescence, defect-band emission, and Lock-in Infrared Thermography (LIT) generally enable the correlation of multi-crystalline silicon defect types. Long Wavelength Infrared (LWIR) thermal imaging has traditionally seen limited application in failure analysis. LWIR cameras are typically uncooled systems using a microbolometer Focal Plane Arrays (FPA) commonly used in industrial IR applications, although cooled LWIR cameras using Mercury Cadmium Tellurium (MCT) detectors exists as well. On the contrary, the majority of the MWIR cameras require cooling, using either liquid nitrogen or a Stirling cycle cooler. Cooling to approximately −196 °C (77 K), offers excellent thermal resolution, but it may restrict the span of applications to controlled environments. Recent developments in LWIR uncooled and unstabilized micro-bolometer technology combined with microscopic IR lens design advancements are presented as an alternative solution for viable low-level leakage (LLL) defect localization and circuit characterization. The 30 micron pitch amorphous silicon type detector used in these analyses, rather than vanadium oxide (VOx), has sensitivity less than 50mK at 25C. Case studies reported demonstrate LWIR enhanced package-level and die-level defect localization contrasted with other quantum and thermal detectors in localization systems.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 141-146, November 1–5, 2015,
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The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 147-151, November 1–5, 2015,
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Accurate and lossless current sensing is vital for high performance multiphase buck converters used in the latest voltage regulation modules (VRMs). A synchronous FET onstate resistance based approach is an alternative topology to DCR based sensing and is compatible with any controller, which requires inductor current information. The MOSFET driver has built-in sense circuitry, which when co-packaged with the MOSFETs reduces total footprint and ease of design. The Powerstage embodiment virtually eliminates the parasitic inductance and resistance between Control and Synchronous power MOSFETS; and using thick copper clips substantially reduce the parasitics associated with the input supply voltage (VIN) and the switch node output voltage (VSW) connections when compared to wire-bonded solutions. This paper presents a novel investigation into a contradictory low on-resistance paradox in a stacked 3D configuration. Through analysis, characterization and simulation the author deciphered the conundrum leading to a root cause explained by a mismatch of internal gain and referenced on-resistance. Building on previous metrology improvements the innovative insights drove analysis toward root-cause.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 350-357, November 9–13, 2014,
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Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 283-291, November 3–7, 2013,
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Performance degradation due to fatigue accumulation from the repetitive switching of high load current is critical to understanding robust power MOSFET product design. In this paper, we present a novel high-current-temperature (HCT) characterization system used to investigate real world powercycling failure mechanisms. The effects of electric current Joule heating, non-uniform temperature distribution and performance deterioration of discrete power devices are discussed. Thermal fatigue of solder joints and thick aluminum wire bonding are common weak spots with regard to power-cycling capability. We report performance failure mechanisms and discuss the superposition of contributing factors in defining root cause. Results discuss various package influences as part of a robust power MOSFET development process.