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Hui Chen
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Proceedings Papers
ITSC 2015, Thermal Spray 2015: Proceedings from the International Thermal Spray Conference, 1001-1012, May 11–14, 2015,
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Rare earth has been widely used in materials manufacturing to improve hardness and toughness. In this paper, conventional, nanostructured and CeO 2 modified WC-12Co powders were sprayed by using HVOF spraying technology. Erosion-corrosion behavior and interaction role of erosion and corrosion of the three coatings in 3.5wt% NaCl solution were investigated. In situ observation method was employed to analyze failure mechanism. The results showed that CeO 2 modified WC-12Co coatings possessed the best erosion-corrosion resistance, which is the worst for the conventional WC-12Co coating. The addition of rare earth CeO 2 into conventional WC-12Co coating can improve the erosion-corrosion behavior. Results suggested that the erosion-corrosion mechanism in the three coatings was dominated by corrosion-enhanced erosion. However, the extent of corrosion enhanced erosion was different.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 79-83, November 14–18, 2010,
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An advanced method for LF (Lead Free) bump sample preparation to improve the surface of sample that can enhance the image of IMC (Inter Metallic Compound), solder grain boundary and micro-crack after TC (thermal cycle) reliability test is proposed. By this advanced method application, LF bump micro-crack location and propagation path can be observed easily for the reliability test fracture failure mechanism study and LF bump crack improvement further.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 280-283, November 4–8, 2007,
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The purpose of this paper is to present a systematic analysis methodology for a newly taped-out High Voltage (HV) product that has encountered a 0% yield issue. In order to identify the root cause and improve the yield, a series of electrical analysis experiments designed to reveal the failure phenomenon of the charge-pumping circuit were applied. Combining spice simulation data, I-V curve measurements, CAFM measurements and nano probing, the difference in resistance for a multi-fingered symmetric device was revealed. A deductive method was then used to conduct layout analysis, and an in-line split experiment was developed to explain the failure phenomenon experienced by the multi-fingered HV symmetric device for a charge-pumping circuit.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 260-263, November 12–16, 2006,
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This paper presents a method of using a conductive atomic force microscope (C-AFM) to characterize a submicron metal fuse that has been blown open inadequately by laser. In order to obtain a proper I-V curve measured using the C-AFM without affecting the incompletely opened fuse, the paper proposes a method of preserving the fuse by coating its surface with spin-on glass. The paper explains how differences in laser cutting machines resulted in the high failure repair rate of customer product despite equivalent energy and spot size settings. Analysis of the fuse bank circuitry on wafers helped to find the critical physical differences between a fully blown and a poorly blown fuse. By overcoming difficulties in preserving the blown fuse failure sites for C-AFM measurement, laser settings could be easily optimized to ensure proper fuse opening.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 412-418, November 12–16, 2006,
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Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.