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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 153-162, October 30–November 3, 2022,
Abstract
View Papertitled, X-Ray Device Alteration Using a Scanning X-Ray Microscope
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for content titled, X-Ray Device Alteration Using a Scanning X-Ray Microscope
Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integrated Circuit (IC) devices. However, upcoming IC architectures based on Buried Power Rails (BPR) with Backside Power Delivery (BPD) networks will greatly reduce the usefulness of these techniques due to the presence of NIR-opaque layers that block access to the transistor active layer. Alternative techniques capable of penetrating these opaque layers are therefore of great interest. Recent developments in intense, focused X-ray microbeams for micro X-Ray Fluorescence (μXRF) microscopy open the possibility to using X-rays for targeted and intentional device alteration. In this paper, we will present results from our preliminary investigations into X-ray Device Alteration (XDA) of flip-chip packaged FinFET devices and discuss some implications of our findings for EFI/EFA.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 248-252, October 31–November 4, 2021,
Abstract
View Papertitled, Backside EBIRCH Defect Localization for Advanced Flip Chip Failure Analysis
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for content titled, Backside EBIRCH Defect Localization for Advanced Flip Chip Failure Analysis
This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 116-121, November 15–19, 2020,
Abstract
View Papertitled, Enabling EFA on Single Die
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for content titled, Enabling EFA on Single Die
Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 245-249, November 15–19, 2020,
Abstract
View Papertitled, Localization and Characterization of Defects for Advanced Packaging Using Novel EOTPR Probing Approach and Simulation
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for content titled, Localization and Characterization of Defects for Advanced Packaging Using Novel EOTPR Probing Approach and Simulation
A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 86-98, November 10–14, 2019,
Abstract
View Papertitled, V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub-14 nm Standard-Cell Logic And Memory
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for content titled, V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub-14 nm Standard-Cell Logic And Memory
High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 244-248, November 10–14, 2019,
Abstract
View Papertitled, Localizing IC Defect Using Nanoprobing: A 3D Approach
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for content titled, Localizing IC Defect Using Nanoprobing: A 3D Approach
This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 460-464, November 10–14, 2019,
Abstract
View Papertitled, Site-Specific Low Angle Plasma FIB Milling for Cross-Sectional Electrical Characterization
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for content titled, Site-Specific Low Angle Plasma FIB Milling for Cross-Sectional Electrical Characterization
This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 7-18, November 6–10, 2016,
Abstract
View Papertitled, SRAM Bitmap Validation Using Laser-Induced Damage for FinFET ICs
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for content titled, SRAM Bitmap Validation Using Laser-Induced Damage for FinFET ICs
Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 161-165, November 6–10, 2016,
Abstract
View Papertitled, Visible Light Probing Sample Thinning Using Targeted Lapping
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for content titled, Visible Light Probing Sample Thinning Using Targeted Lapping
Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 264-266, November 1–5, 2015,
Abstract
View Papertitled, Symptom or Cause? A Case Study
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for content titled, Symptom or Cause? A Case Study
Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2015) 17 (2): 4–9.
Published: 01 May 2015
Abstract
View articletitled, A Through-Silicon Metrology Target for Solid Immersion Lenses, Part II: Other Applications
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for article titled, A Through-Silicon Metrology Target for Solid Immersion Lenses, Part II: Other Applications
This is the second article in a two-part series that explains how to measure the performance of solid immersion lenses (SILs) used for backside imaging and analysis. In Part I, published in the February 2015 issue of EDFA , the authors describe how they modified a frontside metrology target and used it to evaluate a SIL in a backside imaging system, which prompted the development of an unmounted, backside-specific version of the through-silicon target. In Part II, they explain how these new targets, in addition to measuring resolution, are being used to determine the field of view as well as the line spread and edge response of backside imaging systems. They also discuss some of the challenges encountered when using the targets to characterize emission microscopy systems.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2015) 17 (1): 12–20.
Published: 01 February 2015
Abstract
View articletitled, A Through-Silicon Metrology Target for Solid Immersion Lenses, Part I: Metrology Chip and Example
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for article titled, A Through-Silicon Metrology Target for Solid Immersion Lenses, Part I: Metrology Chip and Example
Metrology targets are an essential tool for evaluating the performance of imaging systems and maintaining their accuracy over time. Ideally, the pattern on the target is simple enough that the expected image is intuitive or, at least, easily simulated. Although many such targets exist for frontside imaging, until recently, few if any could be found for backside applications. In this article, the first of a two-part series, the authors explain how they addressed this gap by converting a readily available frontside target for backside use. The conversion process is described step by step in enough detail that it can be replicated in order to convert other frontside targets. Due to the success of the converted target, an unmounted, backside-specific version has subsequently been developed, the availability of which not only eliminates one of the more difficult steps in the original conversion process, but also provides additional benefits. Using one of these newer targets, the authors evaluated a backside imaging system consisting of a laser scanning microscope (LSM) and a solid immersion lens (SIL). The results are presented here along with the criteria used for the evaluation. Other applications of the new metrology target as well as its limitations are discussed in the May 2015 issue of EDFA .
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 322-328, November 3–7, 2013,
Abstract
View Papertitled, Scan-Shift Debug Using LVI Phase Mapping
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for content titled, Scan-Shift Debug Using LVI Phase Mapping
Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 12-17, November 13–17, 2011,
Abstract
View Papertitled, Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing
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for content titled, Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing
A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 5-13, November 14–18, 2010,
Abstract
View Papertitled, Laser Voltage Imaging: A New Perspective of Laser Voltage Probing
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for content titled, Laser Voltage Imaging: A New Perspective of Laser Voltage Probing
Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.