Non-destructive electrical fault isolation (FI) techniques such as emission- and laser-based techniques have been utilized widely for chip-level failure analysis (FA). However, these techniques by themselves can sometimes be inadequate for certain failure modes. In this paper, we present six FA case studies using Time-Domain Reflectometry (Electro-optical terahertz pulse reflectometry) in combination with the traditional FI techniques.

X-ray imaging for both Failure Analysis and In-line Inspection has been utilized widely in the semiconductor industry, especially for surface mount device applications. During the investigation of total ionizing dose (TID) induced degradation of logic ICs with bulk FinFET technology, we observed that the degradation is mainly in the form of an increase in I/O leakage and IDDQ . Using filters during radiation was shown to impact TID. Failure Analysis was performed to localize the excessive current in both I/O leakage and IDDQ.

We report the results of our studies on thermally induced surface topography changes in ultra-thinned silicon flip-chip packaged devices. Previous results showed that over polishing can result in bump topography on the ultra-thinned Si backside. The topographic bumps were found to form over the solder bump locations on the die. Our latest results show that heating exacerbates the topological variation, possibly due to underfill shrinkage caused by additional curing during heating, or plastic deformation caused by underfill and bump CTE mismatch. Our findings are relevant for Visible Light Probing because the induced topography can prevent Solid Immersion Lenses from making the intimate contact necessary for optimum performance.

This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.

This paper presents a backside chip-level physical analysis methodology using backside de-processing techniques in combination with optimized Scanning Electron Microscopic (SEM) imaging technique and Focused Ion Beam (FIB) cross sectioning to locate and analyze defects and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important role during 20-nm process development and yield-ramping.

This paper presents a novel backside de-processing technique for effective failure analysis of advanced multi-level interconnect metallization CMOS ICs with flip chip package.

We investigated and demonstrated the advantages and limitations of several optical methodologies as valuable silicon failure analysis techniques, and how they could be used in a complementary manner to assist in shortening the diagnostic time.

Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.