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1-3 of 3
Hoonchang Yang
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 362-364, October 30–November 3, 2022,
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DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 277-279, November 15–19, 2020,
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As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 477-480, October 28–November 1, 2018,
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The necessity of hot temperature stress is widely recognized as the initial stress methodology to maintain the stability of products from infant defects in device [1, 2]. However, hot temperature stress has a disadvantage in terms of stress uniformity because temperature variation according to stress environment such as chamber, board, and tester accelerates different stress effects per chips. In addition, this stress condition can cause serious reliability problem in the mass production environments. Therefore, the stress temperature should be lowered to minimize the temperature deviation due to the production environments. The reduction of stress temperature cause the lack of stress amount, so optimized stress voltage and time to maintain the stress condition is required. In this study, various stress voltage and time with decreasing temperature were evaluated in consideration of lifetime that unit elements such transistors and capacitors did not degrade by any stress conditions. In addition, it was confirmed that stress uniformity can be improved in the stress condition obtained by the evaluation. Furthermore, the enhanced initial failure screen ability was proven with mass evaluations.