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Heeil Hong
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 187-189, November 12–16, 2023,
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As memory devices decrease in dimensions, particles are found to be a major source of defects in unexpected DRAM failures due to their relatively large size. Among many DRAM defects, cross-defects account for the majority of system failures for a long time. Hard cross-defects are frequently observed in the first test step. Most of these defective cells are repaired with row or column redundancy resources. However, after high voltage and temperature stress, some of the cross-defects can additionally spread to adjacent rows or columns with reduced resistance. Recently, a new type of bridge cross-defect accompanied by row failures has emerged. This can be detected electrically through current measurements of 2 wordline (WL) under active mode. But, these defects are not obvious even after both high temperature and voltage stress. The bridge causes intermittent failure in the row-direction during DRAM operation. This soft 2-WL bridge is considered a serious fault source that can cause uncorrectable error (UE) at the system level even though on-die error correction code (ODECC) is introduced. Therefore, it is very important to find, improve, and develop control methods on such defects for future DRAM enhancement. In this paper, 2-WL defects or extended cross-defect were intensively analyzed through electrical failure analysis (eFA) and physical FA (pFA). Results reveal fine particles as the cause.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 362-364, October 30–November 3, 2022,
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DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 263-268, October 31–November 4, 2021,
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There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 264-266, November 15–19, 2020,
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As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code correction (ECC) modules. In order to screen these failures in the wafer or/and package level electrical tests, high voltage stress methods are necessary. Therefore, accurate stress quantity decided by combination temperature, voltage and time, and effective stress methodologies are essential for high quality and reliability. For a mass production environment, a wafer level burn-in (WBI) can enable multiple word-lines simultaneously and consistently is appropriate. Moreover, we confirmed the actual voltage level on real cells in WBI and optimized stress parameters in terms of time and voltage. Finally, it was proven through the WBI evaluation for over 60k DRAM chips.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 277-279, November 15–19, 2020,
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As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 88-90, November 6–10, 2016,
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As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 94-96, November 6–10, 2016,
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As microelectronic feature sizes are scaled down, the soft failure rate has increased. Additionally the characteristics and distribution of Dynamic Random Access Memory (DRAM) data retention time and write recovery time (tWR) are getting worse. As a result of this failure analysis, we revealed that the major contributors are caused by the interference noise, resultant from decreasing separation distance between nodes and the signal line noise increasing. This paper gives a detailed analysis of the problem caused by the coupling effects. We investigated the cause of soft noise by simulation and proposed calculation of sensing margin change by interference noise. Finally, we expect that a design improvement to reduce the magnitude of interference noise will result in overall improvement when implemented in the test vehicle.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 237-240, November 1–5, 2015,
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The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.