Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.

Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

The scanning capacitance microscope is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope (SCM). Scanning capacitance spectroscopy (SCS) is useful to utilize an SCM to delineate pn junctions in Si devices. This article reports the applications of SCS to Si devices such as CMOS and BiCMOS. SCS is shown to resolve device features on the 10 nm scale for several technologies. Ongoing work includes verifying the reproducibility of SCS measurements and using physical modeling to support the empirical assignment of depletion region width and electrical pn junction position from SCS data. Another technology area where two-dimensional pn junction data is useful is in CMOS device isolation.

This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.