Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

In this study, MCrAlY-Al 2 O 3 composite powders were produced by ball milling and deposited by plasma, HVOF, and cold spraying. The results show that Al 2 O 3 fractions can be well controlled using composite powder due to non-preferential impact debonding of the matrix and Al 2 O 3 . The microstructure of spray powders is well retained in HVOF and cold-sprayed coatings due to the unmelted or partially molten condition of the spray particles. In the case of plasma-sprayed coatings, however, most Al 2 O 3 particles segregate at lamellar interfaces, forming a continuous oxide scale on the splat. The cold-spray coatings exhibit the highest hardness due to the work hardening effect of kinetic deposition.

In this study, WC-CoWC coatings were produced by HVOF spraying using bimodal-structured WC-Co powder with both micro- and nano-sized WC particles. Due to the melting characteristics of the powder during spraying, the microsized particles are retained in the deposit, but the nanosized particles dissolve into the Co matrix, forming a Co-W-C ternary phase. Compared to coatings sprayed from conventional WC-CoWC powder, the bimodal coatings are more resistant to corrosion and wear and are comparable in microhardness.

With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.

Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.

Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.

SEM-based nanoprobing has proven vital in identifying nonvisual failures through electrical characterization in current FA metrology for fault identification. With eight probes used concurrently, the system could have the ability to obtain other important information such as cell stability as well as the static noise margin (SNM). In this work, the cell stability and SNM at different biasing conditions at low electron beam energy (500eV) of a sub-30 nm technology node SRAM device have been characterized. Bit cell stability, static noise margin test as well as leakage study between two adjacent floating wordines were performed on the SRAM samples. Results show that no significant degradation has been introduced during the data acquisition and imaging processes in the SEM. Good resolution imaging with passive voltage contrast can be achieved with low electron voltage (500eV) throughout the nanoprobing process.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

Rapid technology scaling results in ever shrinking device size. As such, sharper nanotips are required for application in nanoprobing systems. In this work, we present a two-step methodology of fabricating tungsten nanotips with radius of curvature down to 20 nm by using and optimized AC electrochemical etching of tungsten in KOH followed by laser irradiation in KOH. Finally we show the application of the fabricated nanotips with different radius of curvature (ROC) for nanoprobing.

In this study, carbide-based cermet (WC-Co, WC-NiCr, Cr 3 C 2 -NiCr) coatings were prepared by thermal spraying and efforts were made to explore the laser remelting effects on the coating microstructure, hardness, adhesion and tribological behavior under different conditions. Results obtained showed that under elected remelting parameters, laser-treated coatings exhibit denser structures and improved microhardness with smaller variability, as well as enhanced adhesion strength between coating and substrate arising from metallurgical element diffusion. In dry sling condition, HVOF sprayed WC-Co coating after laser remelting showed superior wear resistance, however, contrary to the lubricated condition, which may attribute to more lubricant stored in as-sprayed coatings with higher porosity. Solid particle erosion tests suggested that anti-erosion property of plasma sprayed Cr 3 C 2 -NiCr coating by laser remelting are increased, regardless of erosion velocity and angle. Additionally, the wear loss of laser-treated coating increased with erosion velocity, but due to its improved ductility shows no obvious relation to the erosion angle changing from 30 to 90 degree, which is accordance with the wear surface observation and tribological mechanism analysis.

Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.

Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniques are proven effective for localizing soft failures. In this paper, we demonstrate the feasibility of using such dynamic techniques for functional hard failures and design debug applications. We illustrate experimentally the significance of achieving sufficient signal to noise ratio (SNR) before such applications can be realized effectively, due to the large irregular noise that couples through as the functional pattern is run. We adopted a combination of hardware noise reduction and test program modification to overcome this challenge.

The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Electrical characterizations were needed to identify the root cause of leakage issues in IC devices. The methodology required was dependent on the failure mode obtained during testing and global or nano-scale isolations had to be implemented accordingly. As such, challenges encountered in sample preparation or due to detection methodology choices for every isolation technique have to be addressed in order to localize the defective sites.

With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the advantages of sample preparation evenness and efficiency compared to conventional PFA. This technique also offers a better understanding of the failure mechanism and is easier to execute in identifying the vertical short issue.