Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.

Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Deprocessing from the die backside provides a means of circuit inspection especially when the front side of die is fully covered with metallization. One of the most common techniques used is mechanical milling. It can provide good accuracy and consistency in backside preparation. However, the disadvantage of using this technique is the milling process is very time consuming. It takes at least 1-2 hours to complete the thinning and polishing process for only one unit. In addition, the equipment investment cost and later the maintenance cost (e.g. milling tools) is high. Therefore, an alternative way of backside opening is being proposed by chemical etching which is relatively fast and simple. It saves time and cost as the task can be done in less than 10 minutes while at the same time this new proposed method is still able to preserve the electrical functionality of the device.