Physical Failure Analysis (PFA) is essential for SRAM yield learning, especially in new technologies or FAB transfers. For this to be successful, physical coordinates for tested bitcell failures must be accurately calculated and verified. The timeline for this process can vary dramatically based on the extent and complexity of any issues. This paper details the successful use of fault localization on isolated, voltage sensitive failures to achieve confidence in verification of physical location prior to PFA.

Cell aware diagnosis identifies defects within the standard cell as opposed to traditional layout aware diagnosis that identifies the failing standard cell or the area between two standard cells. In a mature technology dominated by random defects, cell aware results pinpoint the cell internal layer drastically reducing the turnaround time for failure analysis. This paper describes a method to enable cell aware diagnosis in a foundry environment, perform a volume diagnosis analysis with RCAD (fail mode pareto) and drive failure analysis with a quick turnaround time for a 14nm customer chip.