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1-8 of 8
Gil Garteiz
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 163-169, October 30–November 3, 2022,
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While 2.5D and 3D solutions continue to drive advancements in the electronics packaging industry, challenges persist with their reliability and qualification. In this paper, we introduce a new technique that may prove valuable for nondestructive, in-situ measurements of package and die warpage. This system allows for the powerful visualization tools of Computed Tomography to be applied to samples at elevated and cryogenic temperatures over a broad temperature range (+125C to -257C).
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 519-521, November 10–14, 2019,
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Characterization of Computed Tomography X-Ray ionizing dose will be presented along with a methodology to protect space bound flight hardware from exceeding total ionizing dose (TID) budget prior to mission completion.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 618-620, November 5–9, 2017,
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In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 631-634, November 5–9, 2017,
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This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 601-605, November 11–15, 2012,
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Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 330-331, November 14–18, 2010,
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Driving yield improvement activities to decrease baseline logic / scan yield fallout is often perceived as a challenging or complex activity. Much of this perception is based on yield or device teams historical interactions with the FA teams on these types of requests. This paper will present our methodology for generating a relatively high volume of scan FA results in a short time frame. This type of high volume scan FA enables real time FA paretos of what is causing scan / logic yield loss.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 273-275, November 12–16, 2006,
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Tower successfully completed a product qualification of its 130nm copper process this year. The key to this achievement was finding and eliminating a dominant failure mechanism, which appeared during HTOL stress. This paper will cover the failure analysis, in-line problem identification, and corrective actions taken that eventually lead to successful product qualification.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 581-584, November 14–18, 2004,
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Designing devices for failure analisys (FA) is becoming increasingly critical as structure geometries and killer defects rapidly decrease in size. Naturally, devices that are designed for FA are much easier to analyze and have a higher FA success rate than those that are not. Several analyses of functional failures in a 0.18um CMOS SRAM are presented in this paper to demonstrate “Design For FA” usefulness and application. Physical analysis methodology is also discussed.