This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 μs to 2 μs. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA) application on soft failure and extends it to hard failure debug. We present the EeLADA methodology and experimental data to demonstrate its feasibility.

A modulated laser beam in the form of a continuous pulse train is explored on Laser Assisted Device Alteration (LADA). We term this pulsed-LADA to differentiate from conventional continuous wave (cw)-LADA. It is found that a duty cycle of less than 0.9 at low frequency above 1 kHz is sufficient to experience significant enhancements in laser stimulation. Following this, a new derivative of LADA technique called Electrically-enhanced LADA (EeLADA) is developed. Experimental results to demonstrate its capability in improving diagnostic resolution and potential application to hard failure debug will be presented.

Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.

A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.

Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.

Wafer level tester-based fault isolation (FI) tool exists back in 2008 but is not widely adopted by industry. This is expected because such tool is commonly known for its primary role in dynamic electrical FI. Since packages are readily available, there is little motivation in using wafers. This paper provides a different perspective to consider such tool as part of a wafer level debug solution to enhance current failure pre diagnostic and diagnosis capabilities, to meet requirements for fast and effective yield ramp. Test cases are presented to support this perspective and a roadmap that guides next generation wafer level FI tool is also proposed at the end of the paper.