As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.

The case study in this paper describes how collaboration between customer design and test teams and a thorough FAB investigation triggered by a detailed electrical analysis using the Atomic Force Nanoprober (AFP) resulted in the effective resolution of a challenging implant related issue on LDMOS structure that caused yield loss. The quick success in this case has led to a shorter yield ramp cycle on this new product for mass production.

This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.

As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.

This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.

It is difficult to simulate functional failures using static analysis tools, therefore, debugging and troubleshooting devices with functional failures present a special challenge for failure analysis (FA) work and often result in a root-cause success rate is quite low. In this paper, the application of advanced FIB circuit edit (CE) processes combined the static FA analysis yielded successful localization of a bipolar junction transistor (BJT) device soft failure. Additional FA techniques were incorporated within the FA flow, resulting in characterization of the electrical behavior of a suspected transistor and detection of an abnormal implant profile within the active area.

This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.

In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.

Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

Fault isolation is a critical step of failure analysis, which is most important for yield improvement for any new microelectronic device manufacturing. Conventionally, electrical faults are isolated by emission microscopy, liquid crystal, LIVA/TIVA and ORBIRCH etc. techniques after final test. As microelectronic devices are becoming more complicated and with multiple metal layers, failure analysis faces more challenges than before. These challenges are even tougher in wafer foundries because little device information is available. This makes yield ramp-up take longer time. Utilizing inline E-beam inspection equipment, the electrical faults can be captured at the source layer rather than after final test. E-beam inspection can be incorporated in the manufacturing line at any critical layer of front end and back-end. This paper describes the in-line E-beam inspection and presents three cases: (1) Gate-oxide issue, (2) Contact issue, and (3) Interconnect issue to demonstrate its application.