It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1][2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.

With the innovations in packaging technologies which have taken place over the last decade, new assemblies often include an increasing number of dies inside a single package. This is exactly what was predicted by the More than Moore’s paradigm: as the integration of ICs increases, the heterogeneity of the devices found in a single package increases. As a result, the number of potential failures which can appear at assembly level has increased exponentially. At present, no technique has been able to precisely localize defects which are deep inside a complex package. For this reason, a new technique for failure localization for three-dimensional structures is needed. In this paper the technique proposed, based on the coupling of magnetic measurements and simulations, is applied to a three-dimensional structure to precisely localize the current path which is buried deep inside it. A new method, based on parameters fittings of magnetic simulations, is then applied in order to accurately evaluate the distance between the current and the sensor.

Defect localization is a very important step in the process of failure analysis for Integrated Circuits. A very important technique, allowing the localization of the defects with a certain degree of precision, is Magnetic Current Imaging. However, this technique has strict limitations related to the working distance and the maximum current magnitude detectable. We overcame these limitations by using a simulation approach, allowing us to sensibly increase the technique resolution and to map currents which are much weaker. This is done by comparing the measurement of the Magnetic Induction Field to a set of simulations of defect assumptions.