High numerical aperture (NA) laser scanning for fault localization requires the use of special lenses aimed at creating a tightly focused laser spot within an integrated circuit. Typically, extrinsic solid immersion lenses are employed that optimize the refraction at the air-silicon surface. In this feasibility study we investigate with both simulations and experiments the use of integrated diffraction lenses for high-NA imaging. We take the limit to ultrathin silicon and discuss the implications for the lens design and performance.

We report on the use of Fresnel lenses in the failure analysis (FA) of actual failures. The design parameters affecting the performance of Fresnel lenses in terms of resolution, magnification, and field of view have been analyzed. It is demonstrated that the magnification depends linearly on the change in focus distance caused by the lens, normalized by the silicon thickness. The focus distance shift that can be obtained with the Fresnel lens is observed to saturate, whose root-cause remains to be investigated. The field of view is shown to increase with the silicon thickness and, to a lesser extent, with the number of lens rings. It has also been shown that these lenses are robust against patterning distortions. The OBIRCh responses of actual device failures before and after lens placement have been compared, demonstrating clearly the increase in magnification, resolution, and the ability to focus light which all translate into a better electrical fault isolation. All in all, this study proves the usefulness of Fresnel lenses for FA purposes and offers clear guidelines that will facilitate proper lens design.

This paper presents a quick, reliable, and fully quantitative method of measuring the intermetallic coverage of copper to aluminium bonding at time zero and post reliability stressing. This method is currently used in select manufacturing quality control processes, as well as during product release procedures. By applying this measurement method after various life-tests, it has been possible to collect information on degradation in the copper aluminium system which is currently being used to make a model of the corrosion mechanism in the copper aluminium system.

Although RIL, SDL and LADA are slightly different, the main operating principle is the same and the theory for defect localization presented in this paper is applicable to all three methods. Throughout this paper the authors refer to LADA, as all experimental results in this paper were obtained with a 1064nm laser on defect free circuits. This paper first defines mathematically what 'signal strength' actually means in LADA and then demonstrates a statistical model of the LADA situation that explains the optimal conditions for signal collection and the parameters involved. The model is tested against experimental data and is also used to optimise the acquisition time. Through this model, equations were derived for the acquisition time needed to discern a LADA response from the background noise. The model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.

In this paper we present a new method to increase the lateral resolution available in laser scanning failure analysis tools. By fabricating a diffractive lens on the back side of the die, the area of the circuit of interest, directly underneath the lens, may be studied with a lateral resolution up to 3.5 times better than without the lens. This method is easily implemented with standard equipment already present in most failure analysis laboratories, and overcomes some significant problems encountered with alternative resolution enhancing schemes.

In this paper a method is presented to remove the silicon substrate from the back of a CMOS chip altogether, whilst leaving gate oxide and silicide intact. This is achieved by grinding the chip until it becomes transparent and then selectively etching the remaining silicon away. The procedure developed is very fast: A 50 mm2 die can be prepared in under an hour, with the gate and silicide of every transistor intact. The method is especially valuable when front-end process features need to be examined over a large sample area. Information can thus be gained with less effort than by using front side deprocessing or cross sections. Several case studies are used to illustrate the effectiveness of the technique and its benefits over deprocessing from the front. These include accurate measurements of gate length (+/- 2 nm) over the entire chip in a 0.18 µm CMOS technology, and applications to investigation of silicide formation.