Physical Failure Analysis (PFA) is essential for SRAM yield learning, especially in new technologies or FAB transfers. For this to be successful, physical coordinates for tested bitcell failures must be accurately calculated and verified. The timeline for this process can vary dramatically based on the extent and complexity of any issues. This paper details the successful use of fault localization on isolated, voltage sensitive failures to achieve confidence in verification of physical location prior to PFA.

Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer SORT functional test. However, upon testing more wafers, it became evident that the wafer center was impacted by abnormal scan logic fallout. The observed yield loss did not correlate with the MIMCAP scribe line Health Of Line (HOL) structures and the failure root cause could not be directly pin pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets allowed identifying a chip design topography issue resulting in a narrower process window compared to the scribe line MIMCAP HOL structure. Thanks to this knowledge the MIMCAP process was further optimized and the wafer center fallout was fully recovered in volume production.

With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

OBIRCH is a static technique for isolating both high and low resistance failures in test structures that continues to be relevant to sub 14nm technologies. While limited resolution is a factor as devices get smaller, an approximate location is adequate for finding obvious defects on sub 14nm technology structures. Its speed is what makes this technique appealing. If the approximate location isn’t good enough, a more time-consuming, higher-resolution technique can be employed. But the use of OBIRCH as a first isolation technique saves considerable time for a high volume FA lab if obvious defects cause the majority of failures. The seven case studies on sub 14nm technology are examples of obvious defects where OBIRCH had adequate resolution for isolation. The OBIRCH results for the first example are compared to the PVC (Passive Voltage Contrast) and EBAC (Electron-Beam Absorbed Current Imaging) findings to illustrate each technique’s strength and weakness.

With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

EBAC is a high-resolution, static technique that can be used for isolating electrical shorts, but it begins to fail for large, interconnected, test structures. In such cases, localization can be achieved when combined with optical localization techniques such as OBIRCH. This paper presents two case studies of subtle, FEOL shorts on a sub-14nm technology that required the resolution of EBAC.

As the technology scales down, SEM (Scanning Electron Microscope) based nanoprobing faces challenges. Transistors are more susceptible to electron beam damage. As SEM energy decreases to prevent damage, imaging resolution degrades, making it increasingly more difficult to position the probe tips on the contacts. Once landed, the probe stability is important to maintain a good electrical connection throughout the measurement time. We review how well one of the latest generation nano probers addresses these challenges on sub 14nm transistors. Results are compared with a previous generation tool to illustrate the improved imaging and stability capabilities.

With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.

Failure analysis for Static Random Access Memory (SRAM) is the major activity in any microelectronic failure analysis lab. Originating from SRAM array structure, SRAM failure can be simple as single bit, paired bit or quad bit failures, whose defect is located at the failure location, or complicated as logic type failure involving WL or BL patterns or entire blocks, whose defect is often not at the failure location. For such SRAM logic type failures, failure analysis is more challenging and detailed fault isolation is necessary prior to physical failure analysis. This paper has demonstrated how to use SRAM decoder scheme knowledge, detailed layout tracing and Photon Emission Microscope (PEM) analysis to deal with the challenges and find the root causes for several cases of SRAM logic type failures.

Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.

This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.

With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.

For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.