This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.

It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.

A hemispherical silicon solid immersion lens (SIL) was used to improve the spatial resolution of front-side thermal IR imaging in lock-in mode. The bottom of the SIL was coneshaped to reduce the footprint of the SIL to the size of the imaged region. Caused by the lock-in operation mode, the detection limit improves by 2-3 orders of magnitude, and scattered light does not limit the image contrast. By using this SIL in combination with an IR camera working in the 3-5 μm wavelength range, a spatial resolution of 1.4 μm was obtained for thermal IR imaging. An automatic SIL positioning facility was constructed to place the SIL exactly in the center of the imaged region and to easily remove it after the detailed investigation.

Lock-in thermography based on an infrared camera has proven to be a useful tool for failure analysis of integrated circuits (ICs). This article discusses four novel technical developments of lock-in thermography. These developments are blackening the IC surface with colloidal bismuth, the synchronous undersampling technique allowing the use of higher lock-in frequencies, displaying the 0deg/-90deg signal as a novel high resolution emissivity corrected image type, and removing the thermal blurring effect by mathematically deconvoluting the 0deg/-90deg; signal. The effect of these techniques is demonstrated by using a regularly working operational amplifier (pA 741) and a damaged capacitor as test devices. It is shown that blackening the IC surface improves the detection sensitivity in metallized regions by up to a factor of 10, whereas the other methods allow improvement of the effective spatial resolution. The article also discusses which of the spatial resolution improvement techniques is most appropriate in different situations.

In this paper new thermographic techniques with significant improved temperature and/or spatial resolution are presented and compared with existing techniques. In infrared (IR) lock-in thermography heat sources in an electronic device are periodically activated electrically, and the surface is imaged by a free-running IR camera. By computer processing and averaging the images over a certain acquisition time, a surface temperature modulation below 100 µK can be resolved. Moreover, the effective spatial resolution is considerably improved compared to stead-state thermal imaging techniques, since the lateral heat diffusion is suppressed in this a.c. technique. However, a serious limitation is that the spatial resolution is limited to about 5 microns due to the IR wavelength range of 3 -5 µm used by the IR camera. Nevertheless, we demonstrate that lock-in thermography reliably allows the detection of defects in ICs if their power exceeds some 10 µW. The imaging can be performed also through the silicon substrate from the backside of the chip. Also the well-known fluorescent microthermal imaging (FMI) technique can be be used in lock-in mode, leading to a temperature resolution in the mK range, but a spatial resolution below 1 micron.