In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

During the early stage of process development, the major activities are yield ramp up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and inhouse diagnostics tools for DFT so in case of failure FA procedures are rather simple and standardized: run EDA tool, get fail location, perform pFA then feedback to process engineering. However in the case of marginal failure FA procedures are generally more complicated. FA engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused by many different reasons. The analysis of marginal fail is of course very important to screen out healthy devices and detect any problem of process technology or design methodology. In this paper, the authors deal with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Throughout these case studies, LADA was successfully used to define the fault location. The reason of device alteration was well explained with further study. It is obvious that LADA is a very effective way to analyze marginal failures in cases where the FA engineer doesn’t have much design information because the results are very intuitive and clear. There is little doubt of LADA results accuracy because LADA is utilizing the tester to make an accurate Pass/Fail decision. LADA results are direct indication of device sensitivity to parametric changes, in our case voltage margin.

This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper also presents a method to detect multiple hold-time faults in the chain using auto generated pattern, real-time on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three steps. First, the chain integrity test is run at the safe voltage. Second, a set of new patterns is created and run at the failing voltage. Finally, the data is shifted out and compared with the simulation result. The data provides the locations of all of the hold-time faults for the selected failing voltage. Combined with silicon voltage probing, the technique allows the analysis to localize the faults and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching.