Failure Analysis labs involved in customer returns always face a greater challenge, demand from customer for a faster turnaround time to identify the root cause of the failure. Unfortunately, root cause identification in failure analysis is often performed incompletely or rushing into destructive techniques, leading to poor understanding of the failure mechanism and root-cause, customer dissatisfaction. Scanning Acoustic Tomography (SAT), also called Scanning Acoustic Microscope (SAM) has been adopted by several Failure Analysis labs because it provides reliable non-destructive imaging of package cracks and delamination. The SAM is a vital tool in the effort to analyze molded packages. This paper provides a review of non-destructive testing method used to evaluate Integrated Circuit (IC) package. The case studies discussed in this paper identifies different types of defects and the capabilities of B-Scan (cross-sectional tomography) method employed for defect detection beyond delamination.

Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.

High quality and reliability are paramount for automotive and other high grade commercial applications. The implementation of scan testing including stuck-at, transition, IDDQ, bridging and cell-aware patterns have all been targeted at reducing the number of defective parts being shipped. These techniques are not always sufficient to achieve sub defective parts per million (DPPM) quality levels. This paper presents a recurring failure mechanism that was encountered on an automotive device and the subsequent efforts to expand upon existing testing methodologies to effectively screen the defective devices using a delta IDDQ method with specific logic inputs and outputs. In effect, this new testing becomes a cell-aware delta IDDQ targeting one specific input condition that was implemented in production with limited test time overhead.

ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.

This paper will present a practical implementation of ATPG testing and diagnosis in Failure Analysis resulting in a fast and efficient iterative ATPG diagnosis and fault isolation. On this implementation, a compact test HW instead of an ATE is used for cost-effective ATPG testing and characterization capability. The advantages of this implementation are combined with ATPG tools to make it possible to achieve a faster and more efficient implementation of iterative ATPG diagnosis, Dynamic Analysis by Laser Stimulation (DALS) analysis or similar techniques. The requirements needed in order to implement ATPG testing and diagnosis in FA lab will be discussed. Success in determining root cause, especially on the complex analysis cases is determined by the complimentary combination of various fault isolation techniques. Knowledge of the fundamentals of these techniques combined with creative thinking process of the analyst leads to the approaches and solutions that maximize the combined advantages of these techniques.

A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.

The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

Dynamic Laser Stimulation (DLS) techniques for Soft Defect Localization (SDL) have been well documented for logic devices [1][2]. More recent literature has broadened the traditional SDL pass/fail mapping by employing multiple device parameters including power analysis [3], spectrum response [4], and other analog variations [5]. A practical and efficient implementation of SDL without the use of synchronization or traditional Automatic Test Equipment (ATE) hardware is presented. A dynamic way of analyzing many parameters of mixed signal and analog ICs can be obtained through the use of a high waveform rate oscilloscope, feedback loop, or discrete comparator. Multiple case studies are shown to illustrate the methodology.