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Efrat Raz
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Proceedings Papers
Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering
Available to Purchase
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 363-367, November 2–6, 2008,
Abstract
View Papertitled, Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering
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for content titled, Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering
The idea behind Destructive Semiconductor Reverse Engineering (DSRE) is to investigate a device in part or as a whole using many of the techniques employed in the physical failure analysis (PFA) field. The device is usually examined for intellectual property/patent protection or competitive analysis purposes. This paper presents a technique for the full layer-by-layer deprocessing of a single semiconductor device using purely mechanical polishing for DSRE or FA. It describes a step-by-step method developed by Raw Science/Datel Design and Development and Gatan for the reliable, purely mechanical deprocessing of individual dice. The paper presents the two modifications made to the process to virtually eliminate the edge effects. A computer controlled mechanical polishing system coupled with a unique customized process allows for the investigation of those one of a kind samples as a whole with 100% success rate.
Proceedings Papers
Sectioning Integrated Circuit Ceramic Packages for Improved Electromigration Failure Analysis
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ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 496-500, November 6–10, 2005,
Abstract
View Papertitled, Sectioning Integrated Circuit Ceramic Packages for Improved Electromigration Failure Analysis
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for content titled, Sectioning Integrated Circuit Ceramic Packages for Improved Electromigration Failure Analysis
This article presents a step-by-step sample preparation method for the cross sectioning of silicon die in a ceramic package without the need for die removal or epoxy encapsulation. The sample preparation includes sawing the package, sample mounting to the polishing stub, and FIB cutting the area of interest and SEM Exam. In addition, a discussion on an automatic polishing method is included. This method is applicable for a broad range of silicon (Si) die package technologies and has also been successfully used on "TSOP" and state-of-the-art microprocessor packages which include the "organic" substrate, the Si die, and the massive copper die lid. The entire failure analysis is done at room temperature, eliminating any questions about sample preparation artifacts. Because the sample is imaged in the SEM at 90 degrees, much improved layer detail and voids microstructure is present in the final image.