In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.

In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.

In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.

High gate to source/drain (S/D) leakage was observed at both failed pins and ET structures with random failure signatures. Detailed TEM failure analysis revealed an abnormal thin Nitrogen-rich nitride layer along the poly gate which extended to the S/D regions. Along the abnormal nitride layer, appreciable Arsenic (As) segregation occurred. The segregated As dopants at these interfaces may form a continuous conducting path, accounting for the gate to S/D leakage mechanism. The preferable As segregation at the Silicon nitride interface may be related to a vacancy-assisted As diffusion process.