Passivation damage, a common failure mode in microelectronics circuitry, can be easily identified by optical inspection in the form of a local 'discoloration' after exposing the die to a chemical that would penetrate through the crack and attacks metal lines. Unfortunately, this process destroys evidence of what damaged the passivation, since it attacks the damaged region. As a result, in many cases, the mechanism by which the passivation damage occurred is unclear. This problem is addressed in this paper by a procedure to examine passivation damage by transmission electron microscopy (TEM) of a cross-section sample prepared from the backside and without exposing the die from the top side. The backside approach was successfully used to assign the root cause of the passivation damage to packaging process. A topside approach to characterize the passivation damaged region can result in destruction of evidence at the defect location.

Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.

For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We recently encountered single bit and massive array failures, which were traced to an electrical short between tungsten contacts. We report here the failure analysis, which involved electrical and physical testing techniques.

Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.