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1-4 of 4
E.L. Principe
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 399-402, November 12–16, 2023,
Abstract
View Papertitled, Complete Compressed Sensing System For Scanning Probe Microscopy
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for content titled, Complete Compressed Sensing System For Scanning Probe Microscopy
An approach to overcome barriers to practical Compressed Sensing (CS) implementation in serial scanning electron microscopes (SEM) or scanning transmission electron microscopes (STEM) is presented which integrates scan generator hardware specifically developed for CS, a novel and generalized CS sparse sampling strategy, and an ultra-fast reconstruction method, to form a complete CS system for 2D or 3D scanning probe microscopy. The system is capable of producing a wide variety of highly random sparse sampling scan patterns with any fractional degree of sparsity from 0- 99.9% while not requiring fast beam blanking. Reconstructing a 2kx2k or 4kx4k image requires ~150-300ms. The ultra-fast reconstruction means it is possible to view a dynamic reduced raster reconstructed image based upon a fractional real-time dose. This CS platform provides a framework to explore a rich environment of use cases in CS electron microscopy that benefit from the combination of faster acquisition and reduced probe interaction.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2019) 21 (4): 60–62.
Published: 01 November 2019
Abstract
View articletitled, A Dedicated Synchrotron Beamline Suite for Enhanced Validation of Integrated Circuits
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for article titled, A Dedicated Synchrotron Beamline Suite for Enhanced Validation of Integrated Circuits
This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2017) 19 (4): 36–44.
Published: 01 November 2017
Abstract
View articletitled, Plasma FIB Deprocessing of Integrated Circuits from the Backside
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for article titled, Plasma FIB Deprocessing of Integrated Circuits from the Backside
Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 285-298, November 5–9, 2017,
Abstract
View Papertitled, Steps Toward Automated Deprocessing of Integrated Circuits
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for content titled, Steps Toward Automated Deprocessing of Integrated Circuits
This paper discusses the development of an extensible programmatic workflow that leverages evolving technologies in 2D/3D imaging, distributed instrument control, image processing, and automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node IC processor chips in combination with SEM imaging and X-ray tomography. Areas as large as 800μm x 800μm were deprocessed using gas-assisted plasma FIB delayering. Ongoing work involves enhancing the workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite.