Power devices technology and in particular devices based on 4H-SiC require a thick metal layer in top to make a source contact and on the backside to make a drain contact. These metal layers are the main problem for fault isolation activities. Up today, many fault isolation techniques do not allow for results, and it is mandatory to remove this layer before performing them. During the metal removal on wafer there is a high probability of damaging the sample or breaking the wafer, especially if the latter is very thin. In this analysis we show a methodology that allows fault isolation analysis, performed on wafers with metal layers, preventing the risks of sample damage induced from preparation.