As memory devices decrease in dimensions, particles are found to be a major source of defects in unexpected DRAM failures due to their relatively large size. Among many DRAM defects, cross-defects account for the majority of system failures for a long time. Hard cross-defects are frequently observed in the first test step. Most of these defective cells are repaired with row or column redundancy resources. However, after high voltage and temperature stress, some of the cross-defects can additionally spread to adjacent rows or columns with reduced resistance. Recently, a new type of bridge cross-defect accompanied by row failures has emerged. This can be detected electrically through current measurements of 2 wordline (WL) under active mode. But, these defects are not obvious even after both high temperature and voltage stress. The bridge causes intermittent failure in the row-direction during DRAM operation. This soft 2-WL bridge is considered a serious fault source that can cause uncorrectable error (UE) at the system level even though on-die error correction code (ODECC) is introduced. Therefore, it is very important to find, improve, and develop control methods on such defects for future DRAM enhancement. In this paper, 2-WL defects or extended cross-defect were intensively analyzed through electrical failure analysis (eFA) and physical FA (pFA). Results reveal fine particles as the cause.

DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.