Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).

This paper presents a study about the invasiveness of 1340 nm continuous wave laser used for electrical failure analysis on 28 nm advanced technologies. It underlines the potential laser-induced degradation for deep submicron technologies that could jeopardize analysis results by modifying physical and chemical properties at substructure level. The impact of laser power on transistor morphology and electrical behavior is studied and the results of this study enable us to setup safe experimental conditions.

The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.

For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.

With the innovations in packaging technologies which have taken place over the last decade, new assemblies often include an increasing number of dies inside a single package. This is exactly what was predicted by the More than Moore’s paradigm: as the integration of ICs increases, the heterogeneity of the devices found in a single package increases. As a result, the number of potential failures which can appear at assembly level has increased exponentially. At present, no technique has been able to precisely localize defects which are deep inside a complex package. For this reason, a new technique for failure localization for three-dimensional structures is needed. In this paper the technique proposed, based on the coupling of magnetic measurements and simulations, is applied to a three-dimensional structure to precisely localize the current path which is buried deep inside it. A new method, based on parameters fittings of magnetic simulations, is then applied in order to accurately evaluate the distance between the current and the sensor.

Dynamic Laser Stimulation (DLS) techniques proved to be very efficient in soft defect localization bringing a lot of information about the device internal behavior. We need to use external parameter measurements such as frequency, delay, voltage etc to perform these techniques. So they can't be used to study internal signal propagation problems in latched device since signals are resynchronized. We will show that we can use the power analysis coupled with DLS techniques set up to characterize soft defect when we don't have a direct access to monitored signal propagation such as in some transistor transition issues. Laser stimulation in addition of power analysis is used to decrypt security codes in security chip, but in failure analysis it is a new way to reach internal information in order to localize soft defects.

The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.

Defect localization is a very important step in the process of failure analysis for Integrated Circuits. A very important technique, allowing the localization of the defects with a certain degree of precision, is Magnetic Current Imaging. However, this technique has strict limitations related to the working distance and the maximum current magnitude detectable. We overcame these limitations by using a simulation approach, allowing us to sensibly increase the technique resolution and to map currents which are much weaker. This is done by comparing the measurement of the Magnetic Induction Field to a set of simulations of defect assumptions.

Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

Defects localization from the IC’s backside using hot spot detection techniques is discussed. Simulations are used to validate the applicability of hot spot detection from the silicon backside and to determine the optimal experimental conditions. The effects of the dissipated power, the substrate thickness and the defect position relative to the chip area are studied. These simulations take into account the thermal dependence of the silicon thermal conductivity. Transient simulations are also performed to evaluate the effect of modulating the power on the backside temperature difference. Backside Liquid Crystal Microscopy as well as Infrared Thermography and Thermal Laser Stimulation results on defective ICs are presented.

The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.