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David Theodore
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Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 205-209, November 9–13, 2014,
Abstract
View Papertitled, Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause
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for content titled, Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause
In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 601-605, November 11–15, 2012,
Abstract
View Papertitled, Application of Scanning Probe Microscopy Techniques with Electrical Modules in Via Related Defects
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for content titled, Application of Scanning Probe Microscopy Techniques with Electrical Modules in Via Related Defects
Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 461-468, November 12–16, 2006,
Abstract
View Papertitled, Vanishing TiN ARC Coating as an Indicator of EOS in Aluminum Top Metal Lines
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for content titled, Vanishing TiN ARC Coating as an Indicator of EOS in Aluminum Top Metal Lines
Multiple parts failed during a 96 hour HAST (highly accelerated stress test) run. Electrical failure occurred on several pins stressed at 48V during the run. Visual inspection identified possible corrosion damage occurring on a top layer aluminum metal line linked to the failed pins. Additionally, significant lengths of this line and metallization at six other sites appeared white and reflective when viewed through an optical microscope. The device technology utilized a TiN ARC. Aluminum metal with a TiN ARC has a dull, amber color when viewed through an optical light microscope, as opposed to bare aluminum, which appears white and shiny. The initial assumption was that the passivation had lifted off during mold compound removal, along with the top TiN ARC layer at these seven locations. SEM inspection found that final passivation film was still intact over these shiny Al lines, but it was cracked extensively. Neighboring Al lines did not show cracked passivation. A hypothesis was generated that suggested that the TiN ARC was not removed, but rather was altered in some way so as to change its optical appearance. The change in the TiN was believed to be due to a combination of factors that resulted from electrical overstressing of the lines during HAST. A series of experiments utilizing FIB cross-sections, Auger mapping, Auger depth profiling, TEM inspection and EDS were used to show that the TiN ARC layer was still present on the affected lines but had been oxidized. The conclusions drawn from this investigation can be used to rapidly determine the root cause of failure through signature analysis. Shiny Al metal lines are easy to see with optical microscopes and are therefore a useful failure analysis tool to identify electrically and mechanically overstressed lines and circuits.
Proceedings Papers
Single Via Deprocessing Techniques to Enable Physical Analysis for Semiconductor Process Integration
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 253-255, November 6–10, 2005,
Abstract
View Papertitled, Single Via Deprocessing Techniques to Enable Physical Analysis for Semiconductor Process Integration
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for content titled, Single Via Deprocessing Techniques to Enable Physical Analysis for Semiconductor Process Integration
Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing; in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example, a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.