Circuit edit (CE) workflows are well established for FIB energies of 30kV and above. The small spot size associated with such energies provides good milling acuity and imaging resolution needed for advanced CE applications. However, with the introduction of FinFET transistors and decreasing technology nodes, the dramatic reduction in STI to gate distance reduction poses some challenges to circuit editing at these high energies. These include transistor performance degradation due to Ga+ implantation as well as significant lateral scattering beyond the Node Access Hole (NAH) as defined by the pattern. In addition, the relatively fast milling speeds may not give enough control to the user to endpoint at the appropriate layer. In this paper, a group of FinFET transistors on a special test chip was edited with the Ga beam at different energies. Transistor performances were then characterized to evaluate any degradation. The resulting characterization revealed how the transistor performance was affected by the injected ion beams and provided a guideline for the low-kV circuit edit workflow. A novel low-kV FIB workflow was proposed to minimize the transistor damage and maintain the IC functionality after the CE process. The workflow was applied to a challenging CE problem on a 5nm FinFET device. This task included step by step backside delayering at 5kV, preparing the sample for the final circuit edit operation at Metal-1. Working at low landing energies (e.g. 5kV) lowers subsurface damage and reduces etching speed, but with trade offs including lower image resolution, milling acuity, sputtering yield and signal to noise ratio (SNR). However, the consequences of these effects can be mitigated by use of appropriate chemistries with closed loop delivery control and extremely low beam currents (≤1pA), in concert with double aperture beam shaping to minimize beam tails. On the 5nm FinFET device, we demonstrate good delayering control by optimization of beam currents, and gas delivery on the Centrios HX circuit edit system from Thermo Scientific.

In a previous study, the authors introduced a novel technique of using low-beam energy Gallium Focused Ion Beam to expose a large area of Shallow Trench Isolation (STI) over a Dynamic Ring Oscillator (DRO) incurring virtually no change of its operating frequency. In this paper, the authors further investigate the influence of extended dose delivery of 5 kV Ga+ after the initial exposure of the STI over a DRO on modern 7 nm process. The motivation of this study is to understand the dynamics between the Ga+ ion interaction at lower beam energies on live and functional devices and the failure mechanism of the device from such interaction. The frequency of the DROs after the initial STI exposure at 5 kV exhibits <1% increase. Additional dosage of lowkV exposure was performed over the exposed STI and its effects on the DRO frequency was monitored. Finally TEM analysis of the irradiated DROs will be analyzed to understand the failure mechanism of transistors.

Good control over beam and chemistry conditions are required to enable uniform delayering of advanced process technologies in the FIB. The introduction of newer, thinner and more beam sensitive materials have made delayering more complicated. We shall introduce a new chemistry for device delayering and present results from both Ga and Xe ion beams showing its improvement over existing chemistries.