Presentation slides for the ISTFA 2024 Tutorial session “Yield Basics for Failure Analysts.”

Presentation slides for the ISTFA 2024 Tutorial session “MOSFET Testing and Interpretation Overview (2024 Update).”

SRAM is often chosen to be the process qualification vehicle during technology development or yield learning vehicle during product manufacturing, and consequently failure analysis of SRAM is the main feedback for process improvement and yield learning. The most common SRAM failure is single bit cell failure. Although its location can be precisely localized by functional test and the defect causing the failure is within the failing bit cell, its failure analysis becomes more and more challenging in advanced technology nodes. As semiconductor technology continuously scales down, SRAM bit cell size and power supply voltage decrease, resulting in increased transistor strength variation and mismatch. SRAM single bit cell soft failures have become more and more common. For such a failure, its defect is usually subtle or even there is not physical defect at most cases. The soft failure is just due to transistor parameter variation. To evaluate the single bit cell soft failure and identify its root cause, electrical nano-probing is an indispensable measure. In this paper, we will first describe the operation of a 6-Transistor (6-T) SRAM single bit cell and three different types of single bit cell soft failures, then discuss the two electrical nano-probing methods for the SRAM single bit cell soft failure.

Presentation slides for the ISTFA 2023 Tutorial session “MOSFET Testing and Interpretation Overview.”

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included. The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated. Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits. The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results. The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.

Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.