Scanning acoustic microscopy (SAM) has been in use for the analysis of small devices, mostly ICs, for quite some time. [1] This paper address the use of the technique on larger objects, such as solar panels, PCBs, and brazed cooling plates, the issues that arise, and solutions to mitigate those issues.

Failure analysis laser inspection tool (FA/LIT) is a tool for the analysis of packaged devices. FA/LIT can routinely expose bond wires for inspection; however, concerns develop for the exposure of stitch bonds, the examination of small trace cracks, and any requirements to maintain electrical functionality of devices. Matching the FA/LIT settings based upon operation and sample material is critical in achieving good exposure of areas of interest with minimal damage. The use of practice samples, or areas away from the area of interest, to verify results before operations on actual FA parts is strongly recommended in this article. The installation of a grounded sample holder has been shown to greatly improve electrical integrity of samples during the laser ablation procedure. Use of the grounding sample holder improved electrical test results from 0% pass to 100% pass in advanced CMOS devices.

Scanning acoustic microscopy (SAM) is a non-destructive tool for analysis of packaged devices. New materials, package configurations, and technologies have required adaptation of standard practices in SAM. The detection of cracked die, voids, or delamination in the underfill or package are standard issues for SAM. SAM can routinely detect large cracks through the central 80% of the die; however, the occurrence of smaller cracks at the edge of the flip chip die is problematic. This article proposes a model in which alteration in the standard SAM parameters, the gain and Time-of-Flight, enable detection of die edge cracks in assembled Flip Chip devices. IR imaging after thinning and polishing of the die confirms the die edge cracks. The SAM analysis can replace the IR imaging for detection of small die edge cracks taking minutes to complete instead of the hours involved in the sample preparation for IR imaging.

Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.