Bond pad metal corrosion was observed during assembly process characterization of a 0.13um Cu microprocessor device. The bond pad consisted of 12kÅ of Al-0.5%Cu atop 9kÅ of Cu, separated by a thin Ta diffusion barrier. The corrosion was first noted after the wafer dicing process. Analysis of the pad surface revealed pitting-type corrosion, consistent with published reports of classic galvanic cell reactions between Al2Cu (theta phase) particles and the surrounding Al pad metal. Analysis of the bond pads on samelot wafers which had not been diced showed higher-thanexpected incidence of hillock and pit hole defects on the Al surface. Statistically designed experiments were formulated to investigate the possibility that the observed pre-saw pad metal defects act as nucleation sites for galvanic corrosion during the sawing process. Analyses of the experimental samples were conducted using optical and scanning electron microscopy, along with focused ion beam deprocessing and energy dispersive X-ray. This paper explores the relationship between the presence of these pre-existing defects and the propensity for the bond pads to corrode during the dicing process, and reviews the conditions under which pit hole defects are formed during the final stages of the Cu-metallized wafer fabrication process. Indications are that strict control of wafer fab backend processes can reduce or eliminate the incidence of such defects, resulting in elimination of bond pad corrosion in the wafer dicing process.

Recently, Motorola was notified that certain of their RFIC devices had failed electrically during Accelerated Life Testing (ALT) at their customer’s board-mounting facility. These devices were assembled in both 8 and 16 lead narrow-body SOIC packages, and had been previously qualified ‘by comparison’ as JEDEC Moisture Sensitivity Level (MSL) 1, indicating that the packages could be shipped without dry packing and left indefinitely at factory-level temperature and humidity, without the need for pre-baking before surface mount reflow. The returned parts exhibited delamination of the mold compound from the die surface, in some cases resulting in wire bond lifting. Since the parts had been shipped as MSL1 for several years in some cases, it was not deemed necessary to investigate whether the customers, Motorola N.S.S. in Fort Worth, TX, and Swindon, U.K., had implemented any changes in their handling procedures which may have impacted the MSL performance of the packages. At the beginning of February, 2000, because of the fact that the SOIC packages were assembled at an external subcontract facility, the issue was brought to the attention of the Motorola External Manufacturing Quality (EMQ) and External Final Manufacturing (eFM) organizations. A containment action was immediately implemented at the assembly site, which consisted of large-scale Scanning Acoustic Microscope (SAM) inspection of the assembled devices, to identify delamination after post mold cure (PMC). A separate series of more in-depth engineering analyses were also initiated, centering on three main areas: 1, Possible die surface contamination; 2, Possible mold compound material issues, and 3, Possible molding process variation. All such activities were conducted with the support and assistance of the IC packaging subcontractor. Results gathered from these activities are summarized below.