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Dane Scott
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Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 505-508, November 11–15, 2012,
Abstract
View Papertitled, VIS-NIR LED Illumination in Backside Circuit Edit and Optical Probing Applications
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for content titled, VIS-NIR LED Illumination in Backside Circuit Edit and Optical Probing Applications
High resolution optical imaging is critical in assisting backside circuit edit (CE) and optical probing navigation. In this paper, we demonstrated improved optical image quality using VIS-NIR narrow band light emitting diode (LED) illumination in various FIB and optical probing platforms. The proof of concept was demonstrated with both common non-contact air gap lenses and solid immersion lenses (SIL).
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 426-430, November 14–18, 2010,
Abstract
View Papertitled, Pulsed Spot Milling and Deposition to Enable Next Generation Circuit Edit Via Development
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for content titled, Pulsed Spot Milling and Deposition to Enable Next Generation Circuit Edit Via Development
Pulsed spot milling (PSM) and deposition (PSD) extends gallium ion beam technology for circuit edit. Similar to continuous spot mill, a single-point ion beam defines the basic milling profile, however, PSM utilizes a high-speed beam blanker to “pulse” the ion beam. This beam modulation replaces beam rastering by introducing a delay time which is fundamentally equivalent to refresh time during a typical scan pattern to enable and manage chemistry adsorption. Vias with a base diameter <50nm have been enabled by PSM in combination with advanced ion column designs, beam control parameters and endpointing techniques.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 110-118, November 15–19, 2009,
Abstract
View Papertitled, Global Die Ultra-Thin Silicon for Backside Diagnostics and Circuit Edit
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for content titled, Global Die Ultra-Thin Silicon for Backside Diagnostics and Circuit Edit
For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.