Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

With the advent of three-dimensional stacked integrated-circuit (3D IC), the functionality, performance and power of semiconductor devices has been elevated to a new level. At the same time, the analytical techniques used in the evaluation of 3D IC must also advance in capability. Some new methodologies, based on FPGA products, have been developed to analyze 3D IC failures, all using conventional FA equipment and innovative techniques to achieve a short turn-around time and high success rate. A few case studies will be presented to show the effectiveness of the methodologies.