A direct bit leakage measurement (DBLM) scheme is proposed and implemented in 8Mb and 32Mb SRAM’s in 45nm and 28nm technologies. It allows, for the first time, direct and nondestructive measurement of various defect induced leakages in each bit in a functional SRAM. It thus enables collection of various defect induced bit leakage data for low-cost and fast failure analysis. It also enables collection of massive bit leakage data for statistical evaluation and location sensitivity assessment.

Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.