The constant size reduction of the elementary structures in integrated circuits (ICs) and their increasing complexity pushes laser probing techniques to their limits. For old technologies these techniques were powerful tools in defects detection and internal analysis, but now the major limitations of the laser spot size implies the understanding of the complex information contained in the reflected beam when it covers an area of multiple elementary structures. Knowing the contribution of each elementary structure covered by the laser spot in the reflected laser beam is the key to have a good analysis and interpretation of the probed area. In this paper we will expose the different parameters that modify the intensity of a laser beam and the contribution of a basic structure covered by a big laser spot size as well as the systematic approach we have built to deal with this challenging reflected laser probe signal from multiple elementary substructures in very deep submicron technologies.

This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

This paper presents the electrical model of an NMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures and from the results of physical simulation using Finite Element Modeling (TCAD). The latter is a useful tool in order to understand and correlate the effects seen by measurement by given a physical insight of carrier generation and transport in devices. This electrical model enables to simulate the effect of a continuous laser wave on an NMOS transistor by taking into account the laser’s parameters (i.e. spot size and power), spatial parameters (i.e. the spot location and the NMOS’ geometry) and the NMOS’ bias. It offers a significant gain of time for experiment processes and makes it possible to build 3D photocurrent cartographies generated by the laser on the NMOS, in order to predict its response independently of the laser beam location.

Limitations of backside optical techniques for failure analysis of dynamically activated devices have underlined the need to extend the capabilities of Dynamic Laser Stimulation techniques (DLS). DLS techniques provide a precise localization of the dynamically failing area, but it lacks timing information as the fault is often related to a specific test vector. Optical probing techniques such as TRE and LVP [1, 2] are hardly applicable on cases with long test loop and for which no preliminary information is available on the time window of interest. Defect localization and electrical tests can be coupled in order to provide more accurate information about the failure, especially vector information in addition to x and y localization. We have developed a Full Dynamic Laser Stimulation (F-DLS) approach based on laser modulation by electro optic modulator to face this challenge. The purpose of this paper is to present DLS limitations, our motivations, comparisons with other DLS extensions, FDLS implementation on our system, application example and future F-DLS developments.

This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.

A key point to guarantee electronic device quality is device qualification. This part of the process is a significant contributor to the time and cost of the development and production of any electronic device. A device is required to perform a task and its operational lifetime is a key issue for the end user. The more sensitive the qualification technique is, the faster marginalities in the device parameters could be observed. Dynamic Laser Stimulation techniques fill this requirement and could be used in conjunction with traditional qualification procedures.

Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.

Several considerations related to the implementation of the thermal laser stimulation method (OBIRCH, TIVA) in a failure analysis laboratory will be discussed. At the CNES (French Space Agency), we implemented this method on a dual system which includes an emission microscope and a laser-scanning microscope. The amplifier used for amplifying the weak voltage or current variations caused by thermal laser stimulation was shown to be a key factor. The design of such a low noise, high gain and fast voltage amplifier is described. From a 3D finite element ANSYS model of the thermal laser stimulation effect combined with three practical case studies we show that thermal laser stimulation is a rapid and precise method for localizing metallic short type faults in ICs. In order to interpret the thermal laser stimulation signal, a simple CMOS inverter model is also presented.

Emission microscopy and thermal laser stimulation (OBIRCH, TIVA) are two key methods for backside failure analysis. They are both dedicated for localizing current leakage faults in ICs. The complementary relationship of these two techniques is illustrated through six practical case studies. Thermal laser stimulation was able to precisely and directly localize defects such as shorts in the IC’s metallic elements that where not readily detectable by emission microscopy. The case studies also illustrate the ability of thermal laser stimulation to detect and physically localize defects in the IC’s polysilicon layers and silicon substrate.

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.