Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

Test coverage of embedded memories is often split between test modes. A BIST solution is typically used to isolate and test the memory array through test specific ports. The functional interconnect between logic and memory is tested with traditional ATPG test modes where a bypass cell on the scan chain is used to clock data through the memory. This approach may miss test coverage if the functional path is different from the test path[1]. Although commercial ATPG tools provide some capability in this area, the most advanced type of fault models which target small delay defects or cross talk faults are not as streamlined as they are for traditional fault models. Additionally, more advanced fault types don’t typically have the same diagnostic capability. In this paper, capabilities are developed for maximizing the effectiveness of test on embedded SRAM interconnects in an ATPG context. Also, a method is outlined to characterize and validate the timing robustness of the memory ports and provide a silicon diagnostic capability for localizing critical paths and isolating physical defects.