We present the first experimental demonstration of on demand bit-level Static Random Access Memory (SRAM) validation and isolation through the exploitation of a continuous wave (CW) 785nm Laser-Induced Fault Analysis (LIFA) system. Through careful test pattern edits and the observation of a simple pass/fail flag, the ability to spatially map the physical location of pre-selected bits in 40nm, 16nm, and 5nm SRAM arrays using correlation units is confirmed. This work demonstrates a novel and highly-efficient methodology for rapid bit-level logical-to-physical identification. It also improves localization efficacy over conventional bitmap validation best-known methods (BKM) which typically rely on post-fail Photo-Emission Microscopy (PEM) and/or Soft Defect Localization / Laser-Assisted Device Alteration (LADA) performed on an actual fail unit. This new technique re-defines the state-of-the-art in SRAM bitmap validation and localization and offers a pathway to significantly improve cycle time for both product bitmap qualification and subsequent root cause identification.

An asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller randomly caused a corrupted clock state that was not recoverable except through a power on reset, or POR. This paper discusses the techniques used to overcome the many obstacles encountered to determine the root cause of the race condition that corrupted the clock state machine registers.

As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.

In this paper, we present our recent applications of scanning capacitance microscopy (SCM) on specific devices with sampling window as small as 100nm. The dopant related root causes were successfully identified on those devices fabricated with 90nm CMOS technology. The key step in our approach is the development of a sample preparation technique that allows us to precisely x-section through a transistor without being affected by focused ion beam (FIB) artifacts. FIB was used to mark the area of interest with high precision, but it did not expose the devices of interest. Optical microscope and atomic force microscope (AFM) were used to inspect the mechanically polished surface, thus avoiding beam effects from FIB or SEM. In the first application, a doping anomaly was identified in a PFET poly gate, in a single bit failed SRAM cell. In the second application, an asymmetry of a PWell implant profile in a window of 150nm was identified as the cause of leakage in a capacitor array. Our approach may be applied to other scanning probe microscopy (SPM) techniques in the same category, i.e., scanning spreading resistance microscopy (SSRM) or scanning microwave microscopy (SMM).

Advanced technologies with higher gate leakage due to oxide tunneling current enable detection of high resistance faults to gate nodes using a straight forward resistance measurement.

OBIRCH analysis is a useful technique for defect localization not only for parametric failures, but also for functional analysis. However, OBIRCH results do not always identify the exact defect location. OBIRCH analysis results must be used in conjunction with other analysis tools and techniques to successfully identify defect locations.

Soft Defect Localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across a die.[1,2,3,4] The technique has proven its usefulness for quickly locating failing nodes for functional fails that are temperature, frequency, and/or voltage dependant. The localized heating from the laser can toggle the pass/fail condition as it sweeps over failing nodes with the aforementioned sensitivity. The technique is instrumental in identifying latent defect locations on conditional fails even though they seldom produce light emissions or liquid crystal hot spots. These fails often manifest themselves after reliability stress or at the customer. The technique can also be applied to support design groups with first silicon analysis of timing race conditions and identification of signals that are speed path limiters. The main challenges associated with the technique are in synchronizing the tester with the Laser Scanning Module (LSM) and ensuring the laser can heat the device enough to overcome the pass/fail threshold temperature of the failing node.