In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.

In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.

In this paper, we present a novel system and method for the automated mapping of pattern and spontaneous photon emission from very large areas of VLSI circuit using Solid Immersion Lens (SIL). To the best of our knowledge, this is the first time that such a technique has been developed and demonstrated on a real chip. The system being presented includes an automation software Application Programming Interface (API) to control the microscope used to acquire the images, an acquisition software that allows to automatically navigate the chip, move (hop) the SIL to the desired location, focus the image after the SIL landing, register the acquired images, and stitch them together to create a high resolution mosaic. In this paper, we will present, for the first time, a real life example involving thousands of images acquired from a 90 nm bulk technology test chip that were used to create a mosaic of more than 25 x 25 images covering a total area of approximately 400 x 400 μm2.

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.