The Attention-Guided Neural Network is designed to analyze periodic SEM images of SRAM. Autoencoder latent features layer is used to reconstruct the crops of the original image. By thresholding the ability of the autoencoder to reconstruct the original image, the defects and artifacts of the original image are automatically located. This approach could be used to detect visual anomalies.

In advanced chip package failure investigations, Electro Optical Terahertz Pulse Reflectometry (EOTPR) simulation emerges as a highly effective fault isolation technique. However, traditional manual methods for generating simulation models face significant challenges, including laboriousness, time consumption, and susceptibility to human error. To address these obstacles, we have developed an automation software script in-house. This script autonomously interfaces with the design database, extracting crucial trace information and generating an optimized equivalent trace model. This automated process markedly enhances the efficiency of EOTPR model simulations, streamlining workflow, standardizing procedures, and reducing the potential for human error. The efficacy of integrating the automation script into the workflow of advanced package failure analysis was demonstrated through two case studies. This integration significantly enhanced productivity and enabled successful root-cause investigation of advanced package failures.

The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.

An autoencoder-based approach is applied to CAFM images of the chip memory. Latent features visualizing highlights the regions, that could be of the interest to estimate the typical failures: missing contact, additional contact, not sufficient contact. Preliminary results are provided.

For decades, device scaling has been the primary driver of the performance boost in integrated circuit (IC) devices. However, this trend has slowed down in recent years due to physical limitations and technical challenges. To continue meeting the ever-increasing demand for high-performance computing, other innovations such as advanced transistor designs and packaging schemes have emerged. Advanced transistors, such as FinFETs and Gate-all-around FET (GAAFETs), have been developed to overcome the limitations of traditional planar transistors, offering higher performance and energy efficiency. Meanwhile, advanced packaging schemes, such as system-in-package (SiP), 2.5D, and 3D packaging, offer higher integration densities, improved thermal management, and faster data transmission. These innovations are crucial in driving the development of high-performance computing, and they will play an essential role in meeting the growing demand for faster and more efficient computing.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.

This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.

This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.

E-beam induced current technique is a fault isolation technique based on SEM-based nanoprobers. Electron beam induced current (EBIC) can help failure analysts quickly identify the defective device with abnormal junction behavior from a relatively large area of interest. Using EBIC, defects can be pin-pointed down to individual Fin, which significantly enhanced the success rate. In this paper, two cases are used as examples to illustrate how this failure analysis (FA) methodology provides a powerful and efficient solution in localizing defective fins. In the first case, a local full bit-line fail was submitted for failure analysis. In the second case, a MOS capacitor parametric test structure designed to monitor gate oxide break down voltage that showed early break down behavior during in-line test. Failure analysis was requested to investigate the root-cause.

Voltage contrast (VC) mode inline E-beam inspection (EBI) at post contact layer provides electrical readout of critical yield signals at an early stage, which could be months before a wafer reaches functional test. Similar to the passive voltage contrast (PVC) technique that is widely used in failure analysis labs, inline VC scanning is based on scanning electron microscopy, where a low keV electron beam scans across the wafer. Conductive atomic force microscopy (CAFM) was successfully implemented as a characterization method for inline VC defects. In this paper, three challenging VC defect analysis case studies are considered: bright voltage contrast (BVC) gate to active short, BVC Junction leakage, and Dark Voltage Contrast gate contact open. Defects exhibiting a hard electrical short, junctional leakage, and open gate contact are used to illustrate how CAFM provides a powerful and comprehensive solution for in-depth characterization of the inline VC defects.

A variety of parametric test structures were designed with the purpose of characterizing parameters tied to failure modes for specific structures, and the electrical test of the parametric test structures are typically conducted earlier inline, which could be months ahead of the functional test. Due to the unique advantages, conductive-atomic force microscopy (CAFM) was introduced to parametric test structure failure analysis during advanced technology development, and has been proven to be a powerful solution to many challenging failure analysis (FA) problems. This paper uses several case studies to illustrate how CAFM can be used to successfully localize defects in challenging parametric test structures that would otherwise be invisible with conventional FA techniques.

Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.

The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.

With a focus on open failure candidates, an extra effort in defining the ease of physical failure analysis (PFA) processing is taken in this paper by closely modeling the PFA processing flow and detailed estimation of the processing cost involved in every step is made. The paper begins with a discussion on the general PFA procedure to process open failure candidates in logic circuits. This is followed by a section that reviews common practice in PFA candidate selection, before proposing the comprehensive selection flow that aims to filter out the easiest candidate in terms of processing cost. This methodology is then evaluated by several case studies and is followed by a discussion on the potential future work. Case studies show that the cost model closely matches with real-world PFA turnaround time and the authors are working toward automating the full flow in software to further improve the efficiency.

This paper highlights the use of nanoprobing as a crucial and fast methodology for failure analysis (FA) in sub 20nm with an improved semi-auto nanoprobing system. Nanoprobing has the capability to localize as well as characterize the electrical behavior of the malfunctioning device for a better understanding of the failure mechanism. It provides a valuable guide to choose a proper physical FA technique to identify the root cause of the failure. This established methodology helps to accelerate the FA turnaround time and improve the success rate. Its application to a few of the front end of line and one back end of line issues is highlighted in the paper.