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1-5 of 5
Christopher Penley
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 101-104, November 12–16, 2023,
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The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 201-204, November 12–16, 2023,
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As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 295-299, November 12–16, 2023,
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In this paper, we discuss and showcase a 2-step defect isolation methodology by combining Focused Ion Beam “circuit editing” (FIB circuit edit) and Passive Voltage Contrast (PVC) imaging. The combo technique is an effective, robust, and time saving method for isolating defects in large area circuit structures for advanced nodes. The application of FIB circuit edits successfully enhanced the PVC efficiency in defect isolation. More importantly, the developed 2-step methodology improves failure analysis (FA) success rate and quality, and reduces FA turn-aroundtime (TAT).
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 347-351, October 30–November 3, 2022,
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Passive voltage contrast (PVC) is a well-known fault isolation technique in differentiating contrast at via/metal/contact levels while focused ion beam (FIB) is a destructive technique specifically used for cross sectioning once a defect is identified. In this study, we highlight a combination technique of PVC and progressive FIB milling on advanced node fin field-effect transistor (FinFET) for root cause analysis. This combo technique is useful when applied on high-density static random access memory (SRAM) structure, especially when it is difficult to view the defect from top-down inspection. In this paper, we create a FA flow chart and FIB deposition/milling recipe for SRAM failure and successfully apply them to three case studies.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 359-361, October 31–November 4, 2021,
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This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM and TEM imaging, found no structural abnormalities. Suspecting that the failures may be due to dopant-related issues, the authors obtained cross sections of both good and bad devices and scanned them in a tunneling AFM. The paper describes the sample preparation process and includes cross-sectional images showing the difference between good and bad transistors. In SRAM areas where no leakage occurred, the fins are well defined and evenly spaced. However, in the area where an emission spot was observed, two of the fins appear to be overlapping, the result of n-well implants that merged.