The direct measurement of the memory state (i.e. bit at “0” or at “1”) on single magnetic tunnel junction (MTJ) in a commercial magnetic random access memory (MRAM) remains challenging. In this paper, we propose a probing approach to investigate the MTJ resistance and by this way determine the memory state. To reach this goal, the MRAM device needs to be prepared to create an electrical access to both sides of the MTJs. The suitable methodology consists in a backside preparation routine that creates a bevel allowing us to access the bottom side of the MTJs through vias and the top side to the bitlines. After that, two approaches are discussed to establish the electrical connection. First described is the nanoprobing technique where the electrical connection is created by two nanometric tips positioned in contact on vias and bitlines thanks to a scanning electron microscope. It is then possible to collect the current flowing through the MTJs and to evaluate the resistance. A resistance around 12 kΩ and 14 kΩ were determined for “0” and “1” bits respectively, which is in agreement with literature. Secondly, these measurements will be compared to those resulting from a near-field probing experiment done in a conductive mode. A resistance around 19 kΩ and 24 kΩ were determined for “0” and “1” bits respectively. The use of both methods allows for a cross-reference between the resistance values and a discussion on the advantages and drawbacks of both probing techniques.

Failure Analysis has to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits mapping channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: a two-transistor cell (2T-cell) from Atmel and a one-transistor cell (1T-cell) from STMicroelectronics.