During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.

Multiple emission microscopy can be used to obtain a comprehensive overview of device emission during IDDQ-test. In this new approach an emission microscopy image is taken for each pattern of the IDDQ-test. Then the extensive amount of images is analyzed for correlation with IDDQ current levels. As a result, for each increased current level concurrent spots can be identified and further analyzed.

The application of lockin phase mapping of modulated reflectance with SIL is discussed in detail, particularly the socalled ghost mapping signal in STI neighboring to active regions. The different lockin phase between active regions and ghost regions showed clearly that both of them have different physical origins. The phase transition between active regions provides an enhancement of spatial resolution for defect localization in scan cell and sub blocks.c

The lock-in phase mapping technique with modulated reflectance is introduced for the first time. With its help, the modulated reflectance mechanisms using thermal laser in operating FETs, particularly in the pinch off region, are clarified. The free carrier absorption mechanism dominates at a high modulation frequency, while thermo-reflectance mechanisms at a low modulation frequency. In the pinch-off region, thermo-reflectance mechanism cannot be neglected due to extremely low free carrier concentration. The modulated reflectance signal was unexpectedly observed at passive poly/oxide/poly capacitance. The advantages of lockin phase mapping in dynamically operating mixed-signal IC devices are shown in several case studies.

The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.

In this paper, the differential and lockin imaging techniques of Dynamic Photon Emission (DPE) were developed by using highly sensitive near-infrared InGaAs camera in time integrated mode. At first, the setup and method for differential imaging of DPE (DI-DPE) are introduced. The unique debug and pinpointing capability of fails of DI-PEM is discussed in combination with two case studies. Based on DI-DPE, the setup and method for Lockin imaging of DPE (LI-DPE) are then developed for such cases where the correlated DPE is enhanced in strong photon emission background. The correlation in LI-DPE can separate the emission spots from different power domains.

A new localization method called MF-TLS is introduced and applied in failure analysis praxis. The method combines local periodic thermal stimulation technique with periodic excitation of the electrical fails. The mixed frequency signal is detected by a lockin amplifier. MF-TLS was demonstrated on fabricated opens in a metal line and shown to be in semi-quantitative agreement with a capacitance modulation model. The technique was also applied to a scan shift problem and produced a higher sensitivity compared with other dynamic TLS methods. Limits and prospects of this new methodology are described.

New developments concerning lock-in phase detection and spectral analysis techniques applied to accessible IC signals are introduced in detail. These techniques combine the thermal laser stimulation (TLS) with the high sensitivity of lock-in to phase variation or the selectable frequency detection in spectrum analyzer. The difference to normal lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the applications to phase related soft-defects and to a design related jitter problem are shown. The power of such techniques for direct mapping a signal path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.

A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.

Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.

In this report our SRAM failure analysis flow based on a two metal SRAM and a six transistor cell design is presented. The basic SRAM failures inside the cell array are considered. With standard SRAM tests, the failing cells are detected and a fail bitmap with the physical location of the failing cells is generated. The SRAM failures are classified by the pattern formation of the fail cells. The main focus is on the analysis of single bit failures. In contrast to the often limited physical preparation of SRAMs, a detailed description of the electrical analysis with microprobes, especially of single bit cells, is given. The electrical cell analysis is not limited to hard fails. Soft fails are also accessible. For the different failure classes of the flow, a detailed description of the preparation and physical localization methods e.g. voltage contrast and electrical characterization methods using microprobes is given. Furthermore, analysis results are presented for the different failure classes.