A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

X-ray imaging for both Failure Analysis and In-line Inspection has been utilized widely in the semiconductor industry, especially for surface mount device applications. During the investigation of total ionizing dose (TID) induced degradation of logic ICs with bulk FinFET technology, we observed that the degradation is mainly in the form of an increase in I/O leakage and IDDQ . Using filters during radiation was shown to impact TID. Failure Analysis was performed to localize the excessive current in both I/O leakage and IDDQ.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.

Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package technologies such as TSV, u-pillar bumping and stacked-die devices. By showing different types of daily Package FA requests, the paper compares & discusses important factors such as turn-around-time (TAT), success yield and results quality. In the end, an outlook is given how recent developments on these techniques will help to establish a new standard FA flow.

Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.

In this paper, investigations on absolute temperature measurements using IR-Thermography of CMOS integrated micro-hot-plates (μHP) are presented. The results of using two different approaches, emissivity correction and black paint coating, are presented and compared with respect to simulation and electrical testing results. In addition, FIB/SEM investigations were used for surface investigations and determination of possible influences to the thermal behaviour by black paint coating process.

With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.

It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.

In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.

In this paper the application of solid immersion lenses (SIL) in combination with Lock-in Thermography will be demonstrated for backside defect localization. The paper will give an introduction into Lock-in Thermography technique and presents a new developed easy-to-use holding system to adapt SIL for high resolution thermal imaging. It will be shown that defect localization can be applied from the backside of the chip up to a silicon thickness of 250µm using the same SIL. The relationship between the bulk silicon thickness and the resulting optical parameters was investigated.

The paper will present an approach for non-destructive localization of thermal active defects at multi chip devices combining the Lock-in Thermography and following local X-Ray inspection. In combination of both methods inner defects in inter chip connections of complex device built ups can be found in a non-destructive way before opening the device. The methods were demonstrated at defective flip chip devices with a high ohmic daisy chain with lots of chip to chip contacts. Subsequently, cross section analysis at located high ohmic contacts was performed in order to find the root cause of the failure.