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Proceedings Papers
Automating Routing of Product Returns for Failure Analysis with Neuro-Symbolic AI
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ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 47-52, October 28–November 1, 2024,
Abstract
View Papertitled, Automating Routing of Product Returns for Failure Analysis with Neuro-Symbolic AI
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for content titled, Automating Routing of Product Returns for Failure Analysis with Neuro-Symbolic AI
Before failure analysis (FA) can start, a product must get from the customer to the correct location, which is not always trivial, especially in larger companies with many FA labs. Automating and optimizing this routing, therefore reducing manual labor, misrouting, and turnaround time, requires the development of problem-solving methods utilizing both explicit and implicit knowledge. The first type refers to known routing rules, e.g., based on lab equipment or certifications, whereas the second type must be induced from available data, e.g., by analyzing customer descriptions using machine learning (ML) methods. Therefore, to solve the routing problem, we suggest a neurosymbolic integration of natural language processing methods into the symbolic context of a logic-based solver. The conducted evaluation shows that the suggested method can reduce the reships by appr. 33% while ensuring the fulfillment of all shipment constraints.
Proceedings Papers
Multimodal Named Entity Recognition for Semiconductor Failure Analysis
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ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 16-22, November 12–16, 2023,
Abstract
View Papertitled, Multimodal Named Entity Recognition for Semiconductor Failure Analysis
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for content titled, Multimodal Named Entity Recognition for Semiconductor Failure Analysis
During the activity in the Failure Analysis (FA) laboratory, all corresponding findings and conclusions are included in a series of documents known as the FA reports. They shall, in the first place, inform the requestor about the analysis results. But additionally, they shall provide information to solve similar cases. Therefore, these documents play a key role in preserving the knowledge acquired by the engineers as they become available for consultation during future works. The different information systems in FA consist of databases, file shares, wikis, or other human-readable forms. However, the heterogeneity of these databases and the large number of independent documents make it inefficient for manual consultation. In this context, this paper proposes an application of Natural Language Processing (NLP) known as Named Entity Recognition (NER), consisting of an AI-based detection of key concepts in textual data in the form of annotations. These annotations can then be used to boost search systems or other AI models.
Journal Articles
Artificial Intelligence Applications in Semiconductor Failure Analysis
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Journal: EDFA Technical Articles
EDFA Technical Articles (2023) 25 (2): 16–28.
Published: 01 May 2023
Abstract
View articletitled, Artificial Intelligence Applications in Semiconductor Failure Analysis
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for article titled, Artificial Intelligence Applications in Semiconductor Failure Analysis
This article provides a systematic overview of knowledge-based and machine-learning AI methods and their potential for use in automated testing, defect identification, fault prediction, root cause analysis, and equipment scheduling. It also discusses the role of decision-making rules, image annotations, and ontologies in automated workflows, data sharing, and interoperability.
Proceedings Papers
A BERT-Based Report Classification for Semiconductor Failure Analysis
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ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 28-35, October 30–November 3, 2022,
Abstract
View Papertitled, A BERT-Based Report Classification for Semiconductor Failure Analysis
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for content titled, A BERT-Based Report Classification for Semiconductor Failure Analysis
Failure Analysis (FA) is a complex activity that requires careful and complete documentation of all findings and conclusions to preserve knowledge acquired by engineers in this process. Modern FA systems store this data in text or image formats and organize it in databases, file shares, wikis, or other human-readable forms. Given a large volume of generated FA data, navigating it or searching for particular information is hard since machines cannot process the stored knowledge automatically and require much interaction with experts. In this paper, we investigate applications of modern Natural Language Processing (NLP) approaches to the classification of FA texts with respect to electrical and/or physical failures they describe. In particular, we study the efficiency of pretrained Language Models (LM) in the semiconductors domain for text classification with deep neural networks. Evaluation results of LMs show that their vocabulary is not suitable for FA applications, and the best classification accuracy of appr. 60% and 70% for physical and electrical failures, respectively, can only be reached with fine-tuning techniques.
Proceedings Papers
Report Classification for Semiconductor Failure Analysis
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ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 1-5, October 31–November 4, 2021,
Abstract
View Papertitled, Report Classification for Semiconductor Failure Analysis
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for content titled, Report Classification for Semiconductor Failure Analysis
In their daily work, engineers in semiconductor Failure Analysis (FA) laboratories generate numerous documents, recording the tasks, findings, and conclusions related to every device they handle. This data stores valuable knowledge for the laboratory that other experts can consult, but being in the form of a collection of documents pertaining to particular devices and their processing history makes it difficult if not practically impossible to find answers to specific questions. This paper therefore proposes a Natural Language Processing (NLP) solution to make the gathering of FA knowledge from numerous documents more efficient. It explains how the authors generated a dataset of FA reports along with corresponding electrical signatures and physical failures in order to train different machine-learning algorithms and compare their performance. Three of the most common classification algorithms were used in the study: K-Nearest Neighbors (kNN), Support Vector Machines (SVM), and Deep Neural Networks (DNN). All of the classification models produced were able to capture patterns associated with different types of failures and predict the causes. The outcomes were best with the SVM classifier and all classifiers did slightly better in regard to physical faults. The reasons are discussed in the paper, which also provides suggestions for future work.
Proceedings Papers
Using Ontologies in Failure Analysis
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ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 23-28, October 31–November 4, 2021,
Abstract
View Papertitled, Using Ontologies in Failure Analysis
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for content titled, Using Ontologies in Failure Analysis
Fault analysis is a complex task that requires engineers to perform various analyses to detect and localize physical defects in semiconductor devices. The process is knowledge intensive and must be precisely documented. In order to ensure unambiguous documentation, engineers must agree on a clearly defined terminology specifying methods, tools, physical faults and their electrical signatures among other things, and it must be stored in a way that is usable for both engineers and software. One possible solution to this challenge is to formalize domain knowledge as an ontology, a knowledge base designed to store terminological definitions. This paper discusses the development of an ontology for electronic device failure analysis that uses a logic-based representation. The latter ensures that terms are interpreted the same way by engineers and software systems, facilitating the automation of tasks such as text classification, information retrieval, and workflow verification.
Proceedings Papers
Ultra-Low Frequency Laser Voltage Imaging of Mixed-Signal Designs
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ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 191-195, November 5–9, 2017,
Abstract
View Papertitled, Ultra-Low Frequency Laser Voltage Imaging of Mixed-Signal Designs
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for content titled, Ultra-Low Frequency Laser Voltage Imaging of Mixed-Signal Designs
During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.
Proceedings Papers
Tester Assisted Multiple Emission Microscopy
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ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 344-348, November 1–5, 2015,
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View Papertitled, Tester Assisted Multiple Emission Microscopy
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for content titled, Tester Assisted Multiple Emission Microscopy
Multiple emission microscopy can be used to obtain a comprehensive overview of device emission during IDDQ-test. In this new approach an emission microscopy image is taken for each pattern of the IDDQ-test. Then the extensive amount of images is analyzed for correlation with IDDQ current levels. As a result, for each increased current level concurrent spots can be identified and further analyzed.
Proceedings Papers
Improved Lock-in Phase Mapping of Modulated Reflectance with SIL
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ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 105-109, November 9–13, 2014,
Abstract
View Papertitled, Improved Lock-in Phase Mapping of Modulated Reflectance with SIL
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for content titled, Improved Lock-in Phase Mapping of Modulated Reflectance with SIL
The application of lockin phase mapping of modulated reflectance with SIL is discussed in detail, particularly the socalled ghost mapping signal in STI neighboring to active regions. The different lockin phase between active regions and ghost regions showed clearly that both of them have different physical origins. The phase transition between active regions provides an enhancement of spatial resolution for defect localization in scan cell and sub blocks.c
Proceedings Papers
Lock-in Phase Mapping of Modulated Reflectance in Dynamically Operating Mixed-Signal IC Devices
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ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 217-222, November 11–15, 2012,
Abstract
View Papertitled, Lock-in Phase Mapping of Modulated Reflectance in Dynamically Operating Mixed-Signal IC Devices
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for content titled, Lock-in Phase Mapping of Modulated Reflectance in Dynamically Operating Mixed-Signal IC Devices
The lock-in phase mapping technique with modulated reflectance is introduced for the first time. With its help, the modulated reflectance mechanisms using thermal laser in operating FETs, particularly in the pinch off region, are clarified. The free carrier absorption mechanism dominates at a high modulation frequency, while thermo-reflectance mechanisms at a low modulation frequency. In the pinch-off region, thermo-reflectance mechanism cannot be neglected due to extremely low free carrier concentration. The modulated reflectance signal was unexpectedly observed at passive poly/oxide/poly capacitance. The advantages of lockin phase mapping in dynamically operating mixed-signal IC devices are shown in several case studies.
Proceedings Papers
Improved Parasitic Fault Modeling for Automatic Analog Fault Simulation
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ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 281-285, November 11–15, 2012,
Abstract
View Papertitled, Improved Parasitic Fault Modeling for Automatic Analog Fault Simulation
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for content titled, Improved Parasitic Fault Modeling for Automatic Analog Fault Simulation
Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.
Journal Articles
Advanced Dynamic Laser-Stimulation Methods Using Lock-In and Mixed-Frequency Techniques
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Journal: EDFA Technical Articles
EDFA Technical Articles (2010) 12 (4): 12–20.
Published: 01 November 2010
Abstract
View articletitled, Advanced Dynamic Laser-Stimulation Methods Using Lock-In and Mixed-Frequency Techniques
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for article titled, Advanced Dynamic Laser-Stimulation Methods Using Lock-In and Mixed-Frequency Techniques
A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.
Proceedings Papers
Differential and Lock-in Imaging of Dynamic Photon Emission and Applications in Failure Analysis
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ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 373-377, November 14–18, 2010,
Abstract
View Papertitled, Differential and Lock-in Imaging of Dynamic Photon Emission and Applications in Failure Analysis
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for content titled, Differential and Lock-in Imaging of Dynamic Photon Emission and Applications in Failure Analysis
In this paper, the differential and lockin imaging techniques of Dynamic Photon Emission (DPE) were developed by using highly sensitive near-infrared InGaAs camera in time integrated mode. At first, the setup and method for differential imaging of DPE (DI-DPE) are introduced. The unique debug and pinpointing capability of fails of DI-PEM is discussed in combination with two case studies. Based on DI-DPE, the setup and method for Lockin imaging of DPE (LI-DPE) are then developed for such cases where the correlated DPE is enhanced in strong photon emission background. The correlation in LI-DPE can separate the emission spots from different power domains.
Proceedings Papers
Combining Time Resolved Emission and Analog Simulation for Fault Localization
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ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 384-388, November 14–18, 2010,
Abstract
View Papertitled, Combining Time Resolved Emission and Analog Simulation for Fault Localization
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for content titled, Combining Time Resolved Emission and Analog Simulation for Fault Localization
In this paper, we describe a fault localization strategy for scan designs based on Time Resolved Photon Emission (TRE) and analog simulation. After characterizing the defect’s electrical footprint using TRE, analog fault simulation is applied. A user - friendly software package with an easy to use interface to scan diagnosis, layout tool and simulator was created.
Proceedings Papers
Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis
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ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 193-197, November 2–6, 2008,
Abstract
View Papertitled, Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis
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for content titled, Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis
A new localization method called MF-TLS is introduced and applied in failure analysis praxis. The method combines local periodic thermal stimulation technique with periodic excitation of the electrical fails. The mixed frequency signal is detected by a lockin amplifier. MF-TLS was demonstrated on fabricated opens in a metal line and shown to be in semi-quantitative agreement with a capacitance modulation model. The technique was also applied to a scan shift problem and produced a higher sensitivity compared with other dynamic TLS methods. Limits and prospects of this new methodology are described.
Proceedings Papers
Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE
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ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 383-389, November 2–6, 2008,
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View Papertitled, Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE
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for content titled, Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE
In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.
Proceedings Papers
Laser Assisted Lock-In Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
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ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 151-155, November 4–8, 2007,
Abstract
View Papertitled, Laser Assisted Lock-In Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
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for content titled, Laser Assisted Lock-In Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
New developments concerning lock-in phase detection and spectral analysis techniques applied to accessible IC signals are introduced in detail. These techniques combine the thermal laser stimulation (TLS) with the high sensitivity of lock-in to phase variation or the selectable frequency detection in spectrum analyzer. The difference to normal lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the applications to phase related soft-defects and to a design related jitter problem are shown. The power of such techniques for direct mapping a signal path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.
Proceedings Papers
Lock-In Assisted Soft Defect Localization (LIA-SDL) and Its Application in Scan Shift Problems
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ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 128-134, November 6–10, 2005,
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View Papertitled, Lock-In Assisted Soft Defect Localization (LIA-SDL) and Its Application in Scan Shift Problems
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for content titled, Lock-In Assisted Soft Defect Localization (LIA-SDL) and Its Application in Scan Shift Problems
A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.
Proceedings Papers
Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
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ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 395-400, November 6–10, 2005,
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View Papertitled, Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
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for content titled, Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.
Proceedings Papers
Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)
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ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 517-520, November 14–18, 2004,
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View Papertitled, Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)
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for content titled, Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)
Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.
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